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Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip USBDP PHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
E.g. on a ROCK 5B following could be observed:
=> usb start
starting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb reset
resetting USB...
[...]
rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout
rockchip_udphy phy@fed90000: failed to init usbdp combophy
rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110.
Can't init PHY1
Bus usb@fc400000: probe failed, error -110
scanning usb for storage devices... 0 Storage Device(s) found
With shared reference counting this is fixed:
=> usb reset
resetting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Orange Pi 5 Ultra is another board in the Orange Pi 5 family.
Orange Pi 5 Ultra uses Rockchip RK3588,
a new generation of octa-core 64-bit ARM processor,
which includes quad-core A76 and quad-core A55.
Features tested on a Orange Pi 5 Ultra 16GB:
- SD-card boot
- eMMC boot
ROCKCHIP_TPL:
https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin
BL31:
https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_bl31_v1.48.elf
Signed-off-by: Niu Zhihong <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable the needed modules so that ROCKUSB can be used to update the
NanoPi R5S.
Signed-off-by: Diederik de Haas <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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In rockchip_sdhci_execute_tuning the variable tuning_loop_counter is
tested for being less than 0. Ensure that it is a signed type by
declaring it as s8 instead of char.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The RK806 PMIC has a bitfield for configuring the restart/reset behavior
(which I assume Rockchip calls "function") whenever the PMIC is reset
either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL
or RESETB pins.
For RK806, the following values are possible for RST_FUN:
0b00 means "Restart PMU"
0b01 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode"
0b10 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode, and simultaneously
pull down the RESETB PIN for 5mS before releasing"
0b11 means the same as for 0b10 just above.
This adds the appropriate logic in the driver to parse the new
rockchip,reset-mode DT property to pass this information. It just
happens that the values in the binding match the values to write in the
bitfield so no mapping is necessary.
For backward compatibility reasons, if the property is missing we set it
to 0b10 (i.e. BIT(7)) like before this commit was merged instead of
leaving it untouched like in the kernel driver.
Note that this does nothing useful for U-Boot at the moment as the ways
to reset the device (e.g. via `reset` command) doesn't interact with the
RK8xx PMIC and simply does a CPU reset.
Considering the upstream Linux kernel left this register untouched until
(assumed) v6.17[1], this is useful for cases in which the U-Boot
bootloader has this patch (and running with a DT with
rockchip,reset-mode property set) and running an upstream kernel before
(assumed) v6.17, or alternatively later without the property in the
kernel DT.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git/commit/?id=87b48d86b77686013f5c2a8866ed299312b671db
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The bootloader for RK3588 Tiger currently forces the PMIC reset behavior
(stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X
which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Signed-off-by: Quentin Schulz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: e82f642b9821384045915dc30e73df7de8424827 ]
(cherry picked from commit d9c568906be166834f4f977bc7f704176bac5b8a)
Reviewed-by: Kever Yang <[email protected]>
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The bootloader for RK3588 Jaguar currently forces the PMIC reset
behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC)
to 0b1X which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Signed-off-by: Quentin Schulz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: ee907113430aa02a8202c91bb574c385ecc28aa2 ]
(cherry picked from commit 8bd14566b75f9409de703a0d2f9a0704b71a7ebe)
Reviewed-by: Kever Yang <[email protected]>
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To make it easier to read the device tree, let's add constants for the
rockchip,reset-mode property values that are currently only applicable
to RK806 PMIC.
Signed-off-by: Quentin Schulz <[email protected]>
[dt-maintainers did not consider this part of the binding, so we're
keeping the header in the devicetree directory]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 304be20e65ca08fc2e9cb58eb939a0054d8a8b81 ]
(cherry picked from commit 0e417bfcbc385c127c7f5ea01df6289aed8325c2)
Reviewed-by: Kever Yang <[email protected]>
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The RK806 PMIC allows to configure its reset/restart behavior whenever
the PMIC is reset either programmatically or via some external pins
(e.g. PWRCTRL or RESETB).
The following modes exist:
- 0; restart PMU,
- 1; reset all power off reset registers and force state to switch to
ACTIVE mode,
- 2; same as mode 1 and also pull RESETB pin down for 5ms,
For example, some hardware may require a full restart (mode 0) in order
to function properly as regulators are shortly interrupted in this mode.
This is the case for RK3588 Jaguar and RK3588 Tiger which have a
companion microcontroller running on an independent power supply and
monitoring the PMIC power rail to know the state of the main system.
When it detects a restart, it resets its own IPs exposed to the main
system as if to simulate its own reset. Failing to perform this fake
reset of the microcontroller may break things (e.g. watchdog not
automatically disabled, buzzer still running until manually disabled,
leftover configuration from previous main system state, etc...).
Some other systems may be depending on the power rails to not be
interrupted even for a small amount of time[1].
This allows to specify how the PMIC should perform on the hardware level
and may differ between hardware designs, so a DT property seems
warranted. I unfortunately do not see how this could be made generic
enough to make it a non-vendor property.
[1] https://lore.kernel.org/linux-rockchip/2577051.irdbgypaU6@workhorse/
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: "Rob Herring (Arm)" <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Lee Jones <[email protected]>
[ upstream commit: 404005d1083997daec7236620b9ba14bccdce449 ]
(cherry picked from commit 8ee72356e9844265334fd344bc05139d1f615c4d)
Reviewed-by: Kever Yang <[email protected]>
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Radxa E20C has a USB OTG Type-C port for Debug and Data.
Add required Kconfig options to use USB gadget features once pending
USB nodes finally lands in dts/upstream by a future sync.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for the PCIe/USB3 combo PHY used in the RK3528 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Jianwei Zheng <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Like Rockchip RK3328, RK3568 and RK3588, the RK3528 also have a single
node to represent the glue and ctrl for USB 3.0.
Use rk_ops as driver data to select correct ctrl node for RK3528 DWC3.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
the phy-rockchip-naneng-combphy driver on RK3528.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The RK3528 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (COMBPHY).
Some board designs may not use the COMBPHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 port early and leave it to the
COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
the board device tree.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Radxa E20C has two main pwm-regulators, vdd_arm and vdd_logic.
Add init-microvolt props to ensure the regulators are initialized at
the recommended power-on sequence voltage instead of at max voltage.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Drop the sdmmc node from soc u-boot.dtsi and instead use the sdmmc node
from rk3528.dtsi with v6.16-dts now merged to dts/upstream.
This cleanup has no intended functional change.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The rk3528-generic target can no longer boot after v6.16-dts was merged
into dts/upstream, and instead end up in a boot loop:
No serial driver found
resetting ...
After Linux commit 34d2730fbbdd ("arm64: dts: rockchip: move rk3528
i2c+uart aliases to board files") there is no longer an alias for
serial0 defined for the U-Boot only rk3528-generic device tree.
Add a board specific aliases node that include the missing serial0 alias
to resolve the boot issue and ensure that stdout-path = "serial0:..."
can be resolved by U-Boot.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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rk3288 is missing fdtoverlay_addr_r.
The new addresses match those used by rk3308.
Tested on Asus TinkerBoard S.
Signed-off-by: Marius Dinu <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Philipp Tomsich <[email protected]>
Cc: Kever Yang <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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GPIO0_B7 is routed to TXI of the on-board CAN transceiver. The
line has a pull-down per SoC default.
This means the CAN transceiver transmits a dominant zero
and blocks the CAN bus until Linux boots and reconfigures the pin.
Let's switch to pull-up as soon as we can (i.e. in SPL).
This cuts down the "bus is blocked" time from 10 seconds to < 1 second.
Of course, to this needs CONFIG_SPL_BOARD_INIT, so enable it
the Jaguar defconfig.
Signed-off-by: Jakob Unterwurzacher <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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ArmSoM-Sige5 adopts the second-generation 8nm high-performance AIOT
platform Rockchip RK3576, with a 6 TOPS computing power NPU and support
for up to 16GB of large memory. It supports 4K video encoding and
decoding, offers rich interfaces including dual gigabit Ethernet ports,
WiFi 6 & BT5, and various video outputs.
Features tested on a ArmSoM Sige5 v1.1:
- SD-card boot
- eMMC boot
- Ethernet
- PCIe NVMe
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for the PCIe/USB3/SATA combo PHYs used in the RK3576 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Jon Lin <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the
phy-rockchip-naneng-combphy driver on RK3576.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for the USB3.0+DP PHY used in the RK3576 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Frank Wang <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for the USB2.0 PHYs used in the RK3576 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Frank Wang <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Like Rockchip RK3328, RK3568 and RK3588, the RK3576 also have a single
node to represent the glue and ctrl for USB 3.0.
Use rk_ops as driver data to select correct ctrl node for RK3576 DWC3.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Update rk3576-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
checkboard() to be able to read information about the running SoC model
and variant from OTP and print it during boot:
U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000)
Model: Generic RK3576
SoC: RK3576
DRAM: 8 GiB
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Implement checkboard() to print current SoC model used by a board when
U-Boot proper is running.
U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000)
Model: Generic RK3576
SoC: RK3576
DRAM: 8 GiB
Information about the SoC model and variant is read from OTP.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add a minimal generic RK3576 board that only have eMMC, SDMMC and USB
OTG enabled. This defconfig can be used to boot from eMMC or SD-card on
most RK3576 boards that follow reference board design.
eMMC and SD-card boot tested on:
- ArmSoM CM5
- ArmSoM Sige5
- FriendlyElec NanoPi M5
- Luckfox Omni3576
- Toybrick TB-RK3576D
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Use 0x350e as the default USB Product ID for Rockchip RK3576, same PID
being used by the BootROM when the device is in MASKROM mode.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The RK3576 SoC contains a RKRNG block that can be used to generate
random numbers using the rockchip_rng driver.
Add compatible for RK3576 to support random numbers:
=> rng list
RNG #0 - rng@2a410000
=> rng
00000000: 36 dd ab 98 ec fb fe d1 cf 36 b3 e1 9b 3d 00 90 6........6...=..
00000010: f5 84 de 75 6b 27 48 9e 13 62 12 6c 50 ca 47 1a ...uk'H..b.lP.G.
00000020: b3 4d fc 43 c5 b5 2d be 07 27 03 26 bb 69 61 2a .M.C..-..'.&.ia*
00000030: 6f 70 01 83 4e ce 91 7a 5a 6c 7c 00 43 87 3e c5 op..N..zZl|.C.>.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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This Kconfig option used spaces and not tabs for indentation. Switch to
tabs.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The rockchip usb gadget driver cannot build without platform specific
headers being available. Express that requirement in Kconfig as well.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance.
Signed-off-by: Da Xue <[email protected]>
Signed-off-by: Christian Hewitt <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources
for the ROC-3328-CC board.
Signed-off-by: Da Xue <[email protected]>
Signed-off-by: Christian Hewitt <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The GameForce Ace is an RK3588S based handheld gaming device.
Signed-off-by: Chris Morgan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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This implements checkboard() to print the current SoC model used by a
board, e.g. one of:
SoC: PX30
SoC: PX30S
SoC: PX30K
SoC: RK3326
SoC: RK3326S
when U-Boot proper is running.
The information is read from the OTP and also the DDR_GRF. There's no
public information as far as I know about the layout and stored
information on OTP but this was provided by Rockchip themselves through
their support channel.
The OTP stores the information of whether the SoC is PX30K or something
else. To differentiate between PX30/RK3326 and PX30S/RK3326S, one needs
to read some undocumented bitfield in a DDR_GRF register as done in
vendor kernel,
c.f. https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr5.1/drivers/soc/rockchip/rockchip-cpuinfo.c#L118-L133.
I do not own a PX30S, nor RK3326/RK3326S so cannot test it works
properly.
Also add the OTP node to the pre-relocation phase of U-Boot proper so
that the SoC variant can be printed when DISPLAY_BOARDINFO is enabled.
This is not required if DISPLAY_BOARDINFO_LATE is enabled because this
happens after relocation. If both are enabled, then the SoC variant will
be printed twice in the boot log, e.g.:
U-Boot 2025.07-rc3-00014-g7cb731574ae6-dirty (May 28 2025 - 13:52:47 +0200)
Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
SoC: PX30 <---- due to DISPLAY_BOARDINFO
DRAM: 2 GiB
PMIC: RK809 (on=0x40, off=0x00)
Core: 293 devices, 27 uclasses, devicetree: separate
MMC: mmc@ff370000: 1, mmc@ff390000: 0
Loading Environment from MMC... Reading from MMC(1)... OK
In: serial@ff030000
Out: serial@ff030000
Err: serial@ff030000
Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
SoC: PX30 <----- due to DISPLAY_BOARDINFO_LATE
Net: eth0: ethernet@ff360000
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Fix NULL pointer dereference that happen when rockchip-inno-usb2 clock
enabled before device probe. This early clock enable call happen in process
of parent clock activation added in ac30d90f3367.
Fixes: 229218373c22 ("phy: rockchip-inno-usb2: Add support for clkout_ctl_phy").
Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting")
Co-authored-by: Jonas Karlman <[email protected]>
Signed-off-by: Alex Shumsky <[email protected]>
Reviewed-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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In tps65941_buck_val and tps65941_ldo_val hex is an unsigned variable
being assigned the return value from a function that returns int. Change
hex to be an int so that the following test for an error as a negative
value will work as expected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
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In order to get the expected result from
rzg2l_usbphy_regulator_get_enable the return expression needs
parenthesis so that the binary and is performed before the double
logical not.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
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In palmas_smps_val and palmas_ldo_val hex is an unsigned variable being
assigned the return value from a function that returns int. Change hex
to be an int so that the following test for an error as a negative value
will work as expected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
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In lp87565_buck_val hex is an unsigned variable being assigned the return
value from a function that returns int. Change hex to be an int so that
the following test for an error as a negative value will work as expected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
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In lp873x_buck_val and lp873x_ldo_val hex is an unsigned variable being
assigned the return value from a function that returns int. Change hex
to be an int so that the following test for an error as a negative value
will work as expected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
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In pmic_reg_read ret is only assigned to inside #if
CONFIG_IS_ENABLED(DM_I2C) so move the test and return ret inside as well
and also guard the declaration of ret with CONFIG_IS_ENABLED(DM_I2C) to
prevent a warning about an unused variable.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
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In axp_init after checking the chip ID there is an else clause that
returns ret. ret is guaranteed to be 0 at this point as the code would
have returned above if not. The next statement is a return 0 so the
return ret is redundant, remove it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
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- Fix a use after free error in cdns3 gadget support in some cases.
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The call to cdns3_gadget_ep_free_request will free priv_req so do the
call to list_del_init which accesses the memory pointed to by priv_req
before the free.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Siddharth Vadapalli <[email protected]>
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