| Age | Commit message (Collapse) | Author |
|---|
|
This series from Fabio Estevam <[email protected]> adds support for
having the environment be found on an NVMe device that contains a FAT
filesystem.
Link: https://lore.kernel.org/r/[email protected]
|
|
Make the interface type check consistent among the other interface types
by checking it agains the ifname string.
The ifname string contains the string returned by env_fat_get_intf(), which
returns the CONFIG_ENV_FAT_INTERFACE value.
No functional change.
Signed-off-by: Fabio Estevam <[email protected]>
|
|
Add support for retrieving the EXT4 environment from an NVME device, the
same way it can be retrieved from MMC, SCSI, or VIRTIO.
To use the EXT4 environment from an NVME device, pass
CONFIG_ENV_EXT4_INTERFACE="nvme" in the defconfig.
Signed-off-by: Fabio Estevam <[email protected]>
|
|
Add support for retrieving the FAT environment from an NVME device, the
same way it can be retrieved from MMC, SCSI, or VIRTIO.
To use the FAT environment from an NVME device, pass
CONFIG_ENV_FAT_INTERFACE="nvme" in the defconfig.
Signed-off-by: Fabio Estevam <[email protected]>
|
|
In dbsc5_read_vref_training the arrays dvw_min_byte0_table and
dvw_min_byte1_table have 128 elements per channel. The variable
vref_stop_index is limited to be a maximum of 128. This means that the
index used to access the arrays must use a test of '< vref_stop_index'
rather than '<= vref_stop_index' in order to prevent out of bounds
accesses to the arrays.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Tested-by: Marek Vasut <[email protected]>
|
|
Chintan Vankar <[email protected]> says:
This series adds bind method for CPSW to avoid explicit probing, removes
explicit probing of CPSW, adds support for Ethernet boot on SK-AM68,
SK-AM62P-LP, J722S, SK-AM69.
Link: https://lore.kernel.org/r/[email protected]
|
|
Add configs required to enable Ethernet boot for SK-AM69.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Add configs required to enable Ethernet boot for SK-AM69.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
This is required to enable spl_net boot on SK-AM69.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot for SK-AM69.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Enable configs required to support Ethernet boot for J722S.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Add configs to enable Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Enable cache for J722s to optimize performance of CPU to access data from
memory.
Reviewed-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Enable config options needed to support Ethernet boot on SK-AM62P-LP.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Add configs for enabling Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.
Signed-off-by: Andreas Dannenberg <[email protected]>
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Enable cache for AM62p to optimize performance of CPU to access data from
memory.
Reviewed-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Andreas Dannenberg <[email protected]>
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Update dev-data and clk-data to enable Ethernet boot using CPSW on
SK-AM62P-LP.
Signed-off-by: Andreas Dannenberg <[email protected]>
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Enable config options needed to support Ethernet boot on AM68-SK.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Add configs for enabling Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
TI's Ethernet switch needs system controllers enabled in R5SPL stage while
booting via Ethernet. Enable SPL_SYSCON config for
CONFIG_TI_AM65_CPSW_NUSS.
Reviewed-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Chintan Vankar <[email protected]>
|
|
This is required to enable spl_net boot on SK-AM68.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot.
Reviewed-by: Bryan Brattlof <[email protected]>
Signed-off-by: Chintan Vankar <[email protected]>
|
|
This reverts commit 35bddf889652081f150f60740618851b5d4817f4.
Bind method of "am65_cpsw_nuss" driver will ensure binding of it's child
driver "am65_cpsw_nuss_ports", and there is no need to probe CPSW driver
explicitly.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
This reverts commit 93c43a8365fae0f188ac091d129542470ddaf62d.
Bind method of "am65_cpsw_nuss" driver will ensure binding of it's child
driver "am65_cpsw_nuss_ports", and there is no need to probe CPSW driver
explicitly.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
This reverts commit e58d9284850fa78d364d264087fe744717963675.
Bind method of am65_cpsw_nuss driver will ensure binding of it's child
driver am65_cpsw_nuss_ports, and there is no need to call CPSW driver
explicitly. Remove explicit probing of CPSW driver for AM62x.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
CPSW driver is defined as UCLASS_MISC driver which needs to be probed
explicitly. Define bind method for CPSW driver to scan and bind
ethernet-ports with UCLASS_ETH driver which will eventually probe CPSW
driver and avoid probing CPSW driver explicitly.
Signed-off-by: Chintan Vankar <[email protected]>
|
|
The Nano's SPI flash stopped working in U-Boot, as the prior stage loaded
U-Boot, the only thing it was used for was save/loading env vars so update
the DT so it can now initialise it. It also drops enabling the old
TEGRA114_SPI driver, as the flash hangs off the faster TEGRA210_QSPI
interface, nothing on the Nano uses the old interface by default so it's
surplus.
Signed-off-by: Peter Robinson <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Reviewed-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
|
|
The Jetson Nano contains all it's firmware on a 4Mb SPI flash, the
allocated size in that flash for U-Boot is 753664 bytes so we need to
ensure the u-boot.bin doesn't exceed that else it will fail.
Add a BOARD_SIZE_LIMIT and drop a few large, and somewhat esoteric, options
to bring us back under that limit.
Signed-off-by: Peter Robinson <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Reviewed-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
|
|
Surface 2 is a Surface-series Windows RT hybrid tablet computer created by
Microsoft. Surface 2 uses a 1.7 GHz quad-core Nvidia Tegra 4 chipset with
2 GB of RAM, features 10.6 inch FullHD ClearType HD screen with 16:9 aspect
ratio and 32/64 GB of internal memory that can be supplemented with a
microSDXC card giving up to 64 GB of additional storage.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
|
|
Neha Malcom Francis <[email protected]> says:
Currently, the inline ECC implementation enables inline ECC across the
entire DDR space. However this is not always required and a more common
ask is to have only a portion of the DDR protected as enabling ECC
impacts read/write performance metrics.
This series aims to modify the logic to firstly support partial inline
ECC in its' most basic form which works for single controllers. Then it
introduces an algorithm to support multi DDR controllers where
interleaving plays a role. Since interleaving is handled by the MSMC, it
only makes sense to have the MSMC decide the inline ECC ranges for each
DDR.
This series also introduces support for multiple partial regions of inline
ECC however due to complexity only support for single DDR is present now.
WIP: A commandline test case patch for verifying the correct behaviour
of inline ECC including partial case. Was targeted for v2 however a little
tricky to make it a general test case especially for multi-DDR cases, so
have not combined it in this series for now.
Testing:
- Memtester runs for J721S2 and J784S4 platforms with and without ECC
enablement runs fine.
- Along with patches that add support for the commandline test (see WIP
note above) J784S4 shows expected behavior for three sets of partial
inline ECC regions (non-overlapping, and after modifying J784S4 to
have single DDR instead of multi-DDR):
https://gist.github.com/nehamalcom/bde7e14e96485e4a188c3af3af6d75d6
Link: https://lore.kernel.org/r/[email protected]
|
|
K3 Inline ECC mechanism can support up to 3 regions of inline ECC, add
this support for single controller.
Signed-off-by: Neha Malcom Francis <[email protected]>
|
|
The existing approach does not account for interleaving in the DDRs when
setting up regions. There is support for MSMC to calculate the regions
for each DDR, so modify k3_ddrss_probe to set the regions accordingly
for multi-DDR systems.
Signed-off-by: Neha Malcom Francis <[email protected]>
|
|
Add support for calculation of the protected regions for each DDR in
multi-DDR systems. Since MSMC is the parent node of the individual DDRs
as well as responsible for their interleaving, it only makes sense for
MSMC to contain the logic for dividing the regions.
Signed-off-by: Neha Malcom Francis <[email protected]>
|
|
In K3 multi-DDR systems, the MSMC is responsible for the interleave
mechanism across all the DDR controllers. Add support for MSMC to obtain
the number of controllers it's responsible for using the DT.
Reviewed-by: Udit Kumar <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
|
|
As we increase the functionalities that the K3 DDRSS sub-system support,
it is becoming more evident that the same logic cannot apply to both
single as well as multiple DDR controller devices. Add
CONFIG_K3_MULTI_DDR to be used to differentiate between the two.
Reviewed-by: Udit Kumar <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
|
|
Instead of defaulting to choosing the entire DDR region when enabling
inline ECC, allow picking of a range within the DDR space using DT to
enable.
It expects such a node within the memory node, in the absence of which
we resort to enabling inline ECC for the entire DDR region:
inline_ecc: protected@9e780000 {
device_type = "ecc";
reg = <0x9e780000 0x0080000>;
bootph-all;
};
Signed-off-by: Neha Malcom Francis <[email protected]>
|
|
The reserved space needed for storing the parity remains the same no
matter the size of the region that is being protected. Add this as a
comment for better code understanding.
Reviewed-by: Udit Kumar <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
|
|
To prevent checkpatch warning once we start using this macro more
frequently, shorten the length of it. While at it, also move the
structure k3_ddrss_ecc_region above k3_msmc so that future patches can
have it as a member of k3_msmc.
Reviewed-by: Udit Kumar <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
|
|
Let ecc_regions[x].start reflect the start of the ECC region in terms of
DDR addressing rather than system addressing. This will make it easier
to extend the usage of the same ecc_regions structure for multi-DDR
systems as well.
Reviewed-by: Udit Kumar <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
|
|
Andrew Goodbody <[email protected]> says:
Smatch reported issues including a derference of a pointer before its
NULL check and the use of an uninitialised variable.
Link: https://lore.kernel.org/r/[email protected]
|
|
In k3_nav_ringacc_probe_dt there can be no error code returned from
dev_read_u32_default so ret is not assigned to and should not be used.
Remove the use of ret from the dev_err call as it is unitialised.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
|
Move the first dereference of ring to after the NULL check has occurred.
This will prevent any possible dereference of NULL.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
|
Andrew Goodbody <[email protected]> says:
Smatch reported two issues, firstly attempting to compare a u8 to a 16
bit macro and secondly a potentially uninitialised variable.
Link: https://lore.kernel.org/r/[email protected]
|
|
In k3_r5f_split_reset and k3_r5f_unprepare ret may not have been
assigned to before the code reaches the return ret at the function exit.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
|
In the struct ti_sci_proc the fields proc_id and host_id are declared as
u8 so cannot be set to nor compared with a macro defined with a value
using 16 bits. Change the macro to only use 8 bits to make the code work
as expected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
|
In order to compile code that uses <asm/atomic.h> on sandbox, we must
provide this header. RISC-V shows us today how to do so with the generic
header implementation, so copy that.
Signed-off-by: Tom Rini <[email protected]>
|
|
Normally, local_save_flags is used as part of the local_irq_* macros, so
remove that as it's unused. Make local_irq_save do something to the
passed variable so that it won't trigger unused variable warnings later.
Signed-off-by: Tom Rini <[email protected]>
|
|
In rt5677_bic_or the call to rt5677_i2c_read returns an int so old
should also be an int to receive that value and then be able to test it
for being negative which would indicate an error.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
|
We are trying to enable -Wmissing-prototypes and this functiion is only
used locally. Mark it as static.
Signed-off-by: Ilias Apalodimas <[email protected]>
|
