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Backported from kernel
commit b89f25ea7892 ("kbuild: use -Werror=implicit-... instead of -Werror-implicit-..."
Signed-off-by: Ilias Apalodimas <[email protected]>
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Backported from kernel
commit ad15006cc784 ("kbuild: clang: choose GCC_TOOLCHAIN_DIR not on LD")
Signed-off-by: Ilias Apalodimas <[email protected]>
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Backported from kernel
commit ba97df45581f ("kbuild: use assignment instead of define ... endef for filechk_* rules")
Signed-off-by: Ilias Apalodimas <[email protected]>
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Backported from kernel
commit 61a0902a06d6a ("kbuild: add -Werror=implicit-int flag unconditionally")
Signed-off-by: Ilias Apalodimas <[email protected]>
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Backport from kernel
commit 42a92bccd213 ("kbuild: add -fno-PIE flag unconditionally")
Signed-off-by: Ilias Apalodimas <[email protected]>
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dev_read_{s,u}32_default"
Quentin Schulz <[email protected]> says:
Out of all the dev_read_*_default functions, only two do not properly
use the type as argument and return type: dev_read_u32_default and
dev_read_s32_default. They both use int instead of u32/s32.
Considering that it's generally not guaranteed that an int is 4 bytes
but also for consistency sake, let's have them use the expected type.
Note that I have not tested this, just stumbled upon that inconsistency
by chance.
Link: https://lore.kernel.org/r/[email protected]
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dev_read_s32_default is for getting an s32 from a Device Tree property
and allows to take a default value if that property is missing.
Considering it calls ofnode_read_u32_default which takes a u32 and
returns a u32, it should do the same instead of using an int, especially
considering that int size is typically architecture-specific, as opposed
to s32/u32.
s32 and u32 being the same size, dev_read_s32* functions calling
ofnode_read_u32_default shouldn't be an issue (at the type level at
least) as the information will be stored appropriately in 4B regardless
of the sign.
This incidentally matches all other dev_read_*_default functions.
Fixes: a1b17e4f4c82 ("dm: core: Add a function to read into a unsigned int")
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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dev_read_u32_default is for getting a u32 from a Device Tree property
and allows to take a default value if that property is missing.
Considering it calls ofnode_read_u32_default which takes a u32 and
returns a u32, it should do the same instead of using an int, especially
considering that int size is typically architecture-specific, as opposed
to u32.
This incidentally matches all other dev_read_*_default functions (except
dev_read_s32_default which will be tackled in the next commit).
Fixes: 47a0fd3bad38 ("dm: core: Implement live tree 'read' functions")
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-stm into next
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/26607
- Add clock and reset drivers support for STM32MP25
- Add STM32H747-Discovery board support
- Add tamp_nvram driver
- Add SPL support and clock tree init to STM32MP13 RCC driver
- Add STM32MP13xx ram support
- Add support for STM32 Image V2.0 for STM32MP13xx
- Fix SYSRAM size on STM32MP13xx
- Fix DBGMCU macro on STM32MP13xx
- Auto-detect ROM API table on STM32MP15xx
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The board includes an STM32H747XI SoC with the following resources:
- 2 Mbytes Flash
- 1 Mbyte SRAM
- LCD-TFT controller
- MIPI-DSI interface
- FD-CAN
- USB 2.0 high-speed/full-speed
- Ethernet MAC
- camera interface
Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add stm32h747i-disco-u-boot DTS file with FMC SDRAM node and its
pinmux settings.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The board includes an STM32H747XI SoC with the following resources:
- 2 Mbytes Flash
- 1 Mbyte SRAM
- LCD-TFT controller
- MIPI-DSI interface
- FD-CAN
- USB 2.0 high-speed/full-speed
- Ethernet MAC
- camera interface
Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
[ upstream commit: 49ba8fc6eab63165639ffbb9f976222d39739cab ]
(cherry picked from commit 19c508dc3d584dc81c0cc6a05576f436022db5b6)
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Add an additional pin map configuration for using the USART1 controller
on the stm32h743 MCU.
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
[ upstream commit: 8e71dfe46a4a1e9505b1a327470f879b63388968 ]
(cherry picked from commit 9d5ec2c9c5d5131e701447c5c32aaf6c688c6e01)
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Add a pin map configuration for using the UART8 controller on the
stm32h743 MCU.
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
[ upstream commit: 47d16ab94b8e5e85aedba3cd22cfdf3877bf1dfb ]
(cherry picked from commit 59621a6472cd6eeb748ed6d6202a21d0f3cc5a83)
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Add support for UART8 by applying the settings specified in the
reference manual RM0433.
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
[ upstream commit: 07aa43adae2363c3734055aeba0789536fa0f8f2 ]
(cherry picked from commit 8fe35c381c7c6db1b95c80be551afada1e9f28e0)
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As stated in the reference manual RM0433, the STM32H743 MCU has
USART1/2/3/6, UART4/5/7/8, and LPUART1. The patches make all the clock
macros for the serial ports consistent with the documentation.
Signed-off-by: Dario Binacchi <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
[ upstream commit: ecab3c40fa49a2073c4c916ebff9496a6b5db7bd ]
(cherry picked from commit aae9a01929183784bf3e2a8001aba408bd0dadf3)
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The board includes an STM32H747XI SoC with the following resources:
- 2 Mbytes Flash
- 1 MByte SRAM
- LCD-TFT controller
- MIPI-DSI interface
- FD-CAN
- USB 2.0 high-speed/full-speed
- Ethernet MAC
- camera interface
Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html
Signed-off-by: Dario Binacchi <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
[ upstream commit: 815d49f61ea049075482161f897aa13e1ae30cbb ]
(cherry picked from commit 06f64674b332c7db4ac56a4dccb0e960d25bea24)
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Allow expanding possible configurations for the same peripheral,
consistent with the scheme adopted in Linux.
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Torgue <[email protected]>
[ upstream commit: 6a36dca4375fce51b627f5a985a79fc8b8bd7f55 ]
(cherry picked from commit 9a72c83f2e670087ae2d6dc54d2926f16c6762d0)
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TAMP backup registers will be exposed as nvmem cells.
Each registers ([0..127] for STM32MP2, [0..31] for STM32MP1) could be
exposed as nvmem cells under the nvram node in device tree
Signed-off-by: Simeon Marijon <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Add support for generating STM32 Image V2.0, which is used by STM32MP13xx.
The image header layout is similar to STM32MP15xx STM32 Image V1.0, but is
different enough to justify duplicate functions to generate the v2 image.
This code at least attempts to align the V1 and V2 image handling where
possible.
Signed-off-by: Marek Vasut <[email protected]>
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Add support for configuring DRAM controller on STM32MP13xx SoC.
The DRAM controller is basically identical to the DWC controller
on STM32MP15xx SoC, except the bus width is reduced from 32bit to
16bit and a few registers and bits are therefore not present.
Handle the difference by factoring these parts out. Use IS_ENABLE()
as much as possible to assure code which is not enabled on builds
for a single SoC gets compiled out. Handle the different offset of
RCC_DDRITFCR register and missing DDRC2 clock the same way.
Signed-off-by: Marek Vasut <[email protected]>
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Add SPL support and clock tree init to STM32MP13 RCC driver. This
consists of two parts, make SCMI into an optional dependency and
add clock tree initialization. The SCMI dependency is made optional
first by registering the few core clock provided by SCMI clock as
fixed clock, and second by letting the clock core parse out the
clock configuration from SoC registers. The clock initialization
code is derived from STM32MP15xx clock tree initialization code,
which is almost identical, except for the use of new PLL2000 for
PLL1 on STM32MP13xx .
Signed-off-by: Marek Vasut <[email protected]>
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Fix basic typo, missing t in security . No functional change .
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The ROM API table location is passed to the SPL by BootROM in register r0,
make use of this, store the content of r0 and later use it to access the
ROM API table to determine current boot device.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The DBGMCU block is available at address 0x50081000 both on STM32MP13xx
and on STM32MP15xx . There is no reason to limit the DBGMCU macro being
set only on STM32MP15xx , remove the ifdeffery.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The STM32MP13xx has only 128 kiB of SYSRAM starting at address 0x2ffe0000 .
The STM32MP15xx has 256 kiB of SYSRAM starting at address 0x2ffc0000 . Make
sure both SoCs configure ARMV7_SECURE_BASE correctly . Define the SYSRAM
base in stm32.h to be consistent with the STM32MP15xx macro.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Drop a space after tab, no functional change.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Due activation of SCMI, we need to increase SYS_MALLOC_F_LEN value
to avoid following message:
U-Boot 2025.04-01224-g75b77a2a6d31-dirty (Apr 25 2025 - 11:23:30 +0200)
alloc space exhausted ptr 400040 limit 400000
alloc space exhausted ptr 400020 limit 400000
alloc space exhausted ptr 400060 limit 400000
alloc space exhausted ptr 400060 limit 400000
Set SYS_MALLOC_F_LEN to 0x60000 to fix this issue.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Due SCMI update to protocol v2.0, we need to increase
SYS_MALLOC_F_LEN value to avoid following message:
alloc space exhausted ptr 200040 limit 200000
Set SYS_MALLOC_F_LEN to 0x210000 to fix this issue.
Signed-off-by: Patrice Chotard <[email protected]>
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SCMI clocks are now available, switch from fixed to SCMI clocks.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Implement STM32MP25 reset drivers using stm32-core-reset API.
This reset stm32-reset-core API and will be able to use DT binding
index started from 0.
This patch also moves legacy reset into stm32 directory reset.
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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In RCC the ops of the CCF registered CLK device can be called directly,
this patch avoid recursive call of clk_ function done by CCF clock
framework which update the clock information, for example
clk_enable is called 2 times, clkp->enable_count is increased 2 times.
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add private uclass data for "stm32-usbphyc-clk" as it is not done
by the driver model.
This clk struct is needed by CCF to save the unique id used to identify
each clock.
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Each clock identifier needs to be unique when CCF is activated,
and it is not respected today by SCMI clock driver.
This patch supports a unique clk id by using the uclass API
clk_get_id() / dev_clk_dm() and by activating by default
CONFIG_CLK_AUTO_ID with CCF which adds an offset to the SCMI
clock identifiers.
After this patch, the SCMI clock driver can coexist with other
clock provider without conflict, they can share internal identifier
[0..N] defined in their binding and the clock ID = 0
(reserved for dummy clock) is no more used.
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Update CLK ID to avoid 0 id, used for dummy clock with CCF
and to allow selection by clk_get_by_id, used to
get private data associated to the UCLASS_CLK device
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Update the existing test dm_test_clk_ccf() with new CLK_ID macro.
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Update the sandbox driver to allow support of the
CONFIG_CLK_AUTO_ID by using the new API clk_get_id()
to get the internal SANDBOX identifier.
With CONFIG_CLK_AUTO_ID, clk->id have the also seq identifier.
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add a new config CONFIG_CLK_AUTO_ID to support a unique clk id
for all the clock providers, managed by clk uclass, when the clock
reference arg[0] is the same.
When the CONFIG is activated, the clock id is limited to the lower
CLK_ID_SZ = 24 bits in default clock xlate function
and the sequence number + 1 of the clk provider device is
added for the 8 higher bits.
We use sequence number + 1 to avoid the "dummy" clock id = 0,
used for invalid clock when CCF is activated.
When this config is activated, the new function clk_get_id()
should be used to get back the internal reference to clock
for the each clock provider.
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Check clock security to avoid access at boot time.
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add clock driver support for STM32MP25 SoCs.
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Valentin Caron <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Since clock protocol 2.0, SCMI specification add an option field
"clock_enable_delay" to CLOCK_ATTRIBUTES command.
scmi_read_resp_from_smt() will return an error ("Buffer too small") as
the message length coming from the SCMI server is not the same as expected.
So implement a condition to SCMI clock protocol version to change the
length of the expected message.
Signed-off-by: Valentin Caron <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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One more board to support, this time Retronix Sparrow Hawk based on
Renesas R-Car V4H SoC . This is board support, so master branch should
be fine. The DT in dts/upstream/ is a backport from Linux, and will
disappear on next DT sync.
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https://source.denx.de/u-boot/custodians/u-boot-tpm into next
CI: https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/26601
Updates from Simon cleaning up some tests, with the intention of being used
in sandbox and actual hardware.
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Add Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0
(R8A779G3) SoC. This is a single-board computer with single gigabit ethernet,
DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD ports,
micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe SSD,
debug UART and JTAG.
DT is imported from Linux next commit:
a719915e76f2 ("arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support")
Signed-off-by: Marek Vasut <[email protected]>
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Introduce weak renesas_dram_init_banksize() function which is meant
to be used to adjust DRAM bank sizes after the common Renesas board
DRAM bank handling code finished. This is mainly meant for boards
which ship with multiple DRAM size options, which can be detected
at runtime. This allows such boards to ship with single U-Boot
binary on all boards.
Signed-off-by: Marek Vasut <[email protected]>
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These tests have been failing for some months. Disable them so that a CI
run can pass on coral. Further work will be needed to see how to make
them pass.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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These don't seem to be needed.
Add a few notes about what to do next. Also mention parallel tests in
at the top of thefile.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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Some of the Python tests are a pain because they don't reset the TPM
state before each test. Driver model tests do this, so convert the
tests to C.
This means that these tests won't run on real hardware, but we have
tests which do TPM init, so there is still enough coverage.
Rename and update the Python tpm_init test to use 'tpm autostart',
since this fully initializes the TPM and performs the self tests.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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Add support for the self-test continue command in the TPM v1.2 emulator,
to match the functionality in the TPM v2 emulator.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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Prepare v2025.07-rc4
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