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Greg Malysa <[email protected]> says:
This series adds all of the supported peripheral drivers for the sc5xx
series of SoCs from Analog Devices and other drivers that are used by
the evaluation kits, such as a GPIO expander used by the EZLITE carrier
boards. This series passes gitlab CI tests.
Link: https://lore.kernel.org/r/[email protected]
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Co-developed-by: Greg Malysa <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
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This adds support for the ADI-specific SPI driver present in the ADI
SC5xx line of SoCs. This IP block is distinct from the QSPI/OSPI block
that uses the Cadence driver. Both may be used at once with appropriate
pin muxing configuration.
Co-developed-by: Greg Malysa <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
Co-developed-by: Angelo Dureghello <[email protected]>
Signed-off-by: Angelo Dureghello <[email protected]>
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Co-developed-by: Piotr Wojtaszczyk <[email protected]>
Signed-off-by: Piotr Wojtaszczyk <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
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This adds the ability to load ldr-formatted files to the SHARC
coprocessors using the rproc interface. Only a minimal subset
of rproc functionality is supported: loading and starting
the remote core.
Secure boot and signed ldr verification are not available
at this time through the U-Boot interface.
Co-developed-by: Greg Malysa <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Co-developed-by: Piotr Wojtaszczyk <[email protected]>
Signed-off-by: Piotr Wojtaszczyk <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
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Add a rudimentary MDMA driver for the Analog Devices SC5xx SoCs,
primarily intended for use with and tested against the QSPI/OSPI
IP included in the SoC.
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Co-developed-by: Nathan Barrett-Morrison <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
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Co-developed-by: Greg Malysa <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The ADI SC598 includes a Designware QoS 5.20a IP block. This
commit adds support for using the existing ethernet QoS driver
with the SC598 SoC.
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Co-developed-by: Nathan Barrett-Morrison <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
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Co-developed-by: Greg Malysa <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Co-developed-by: Angelo Dureghello <[email protected]>
Signed-off-by: Angelo Dureghello <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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This adds support for the MUSB-based USB controller found in the
Analog Devices SC57x and SC58x SoCs.
Co-developed-by: Greg Malysa <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
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This adds support for the ADP588 GPIO expander from Analog Devices. It
is accessed over I2C and provides up to 18 pins. It is largely a port of
the Linux driver developed by Michael Hennerich
<[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
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This adds support for using the GPIO pins on the SC5XX family of SoCs
from Analog Devices.
Co-developed-by: Nathan Barrett-Morrison <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
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This adds the necessary dt-bindings and documentation to use the ADI
SC5xx pinctrl driver in a device tree. It is not yet available upstream
in the Linux kernel. Eventually, it will be moved there.
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
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This adds support for pin configuration on the Analog Devices SC5XX SoC
family. This commit is largely a port of the Linux driver, which has not
yet been submitted upstream.
Co-developed-by: Nathan Barrett-Morrison <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
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This series from Patrick Rudolph <[email protected]> fixes
an issue with how we treat PCIe vs PCI in some cases and fixes the
qemu-arm-sbsa reference platform support.
Link: https://lore.kernel.org/r/[email protected]
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Enable PCI enumeration by default to get the Bochs display driver up
and running before the boot medium is scanned.
This is just to enhance the user-experience while booting the machine.
TEST: U-Boot logo, version, log output and the U-Boot shell is visible
on the display device.
Signed-off-by: Patrick Rudolph <[email protected]>
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qemu's sbsa-ref is always using a 64bit CPU and the PCI prefetch MMIO
window is located above 4GiB, thus always enable SYS_PCI_64BIT.
Signed-off-by: Patrick Rudolph <[email protected]>
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Legacy PCI devices, like qemu's Bochs VGA device, are allowed to have
prefetchable 32-bit BARs, while PCIe devices are not allowed to have
32-bit prefetchable BARs. Typically prefetchable BARs are 64-bit and
typically the prefetch MMIO window is also 64-bit and placed above
4GiB, as it's the case on qemu sbsa-ref.
Currently the U-Boot code assumes that prefetchable BARs are
64-bit BARs and always tries to assign them into the prefetch
MMIO window.
When a 32-bit BAR is marked as prefetch, but the prefetch area is
not within the first 4GiB of the address space, then downgrade the
BAR and place it in the non-prefetch MMIO window.
For prefetch BARs there's no downside on being placed in non prefetch
MMIO areas, besides the possible slower performance when a driver tries
to map it Write-Combine.
TEST: Fixes pci_auto on QEMU sbsa-ref fails to autoconfigure BAR0.
Signed-off-by: Patrick Rudolph <[email protected]>
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Since commit 948da7773e34 ("arm: Add new config option ARCH_VERY_EARLY_INIT")
debug_uart_init() is called respectively in crt0.S and crt0_64.S.
That means that _debug_uart_init() is called for all STM32MP platforms
even for those which doesn't support SPL_BUILD.
So restrict _debug_uart_init() execution for platforms which can have
SPL_BUILD enabled (STM32MP1 platform only).
It's more needed to call debug_uart_init() in stm32mp1/cpu.c.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Vikas has left STMicroelectronics several years ago.
Put myself as maintainer of stm32f746-disco board.
Signed-off-by: Patrice Chotard <[email protected]>
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The pwm source TIM1_CH3N channel (on PE12) in inverted polarity mode
will be used to manage the brightness of the panel backlight on
STM32MP135F-DK.
Signed-off-by: Cheick Traore <[email protected]>
Reviewed-by: Fabrice Gasnier <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Enable the following configs:
* CONFIG_MFD_STM32_TIMERS: enables support for the STM32 multifunction
timer
* CONFIG_DM_PWM: enables support for pulse-width modulation devices
* CONFIG_CMD_PWM: enables 'pwm' command to control PWM channels
* CONFIG_PWM_STM32: enables support for the STM32 PWM devices
Signed-off-by: Cheick Traore <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add driver to support pwm on STM32MP1X SoCs. The PWM signal is generated
using a multifuntion timer which provide a pwm feature. Clock rate and
addresses are retrieved from the multifunction timer driver.
Signed-off-by: Cheick Traore <[email protected]>
Reviewed-by: Fabrice Gasnier <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add support for STM32MP timer multi-function driver.
These timers can be use as counter, trigger or pwm generator.
This driver will be used to manage the main resources of the timer to
provide them to the functionnalities which need these ones.
Signed-off-by: Cheick Traore <[email protected]>
Reviewed-by: Fabrice Gasnier <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-tegra into next
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https://source.denx.de/u-boot/custodians/u-boot-tegra into next
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into next
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The value written to the RFLR register includes the length of the CRC
data at the end of each Ethernet frame. So we need to increase the value
written to this register to ensure that we can receive full size frames.
While we're here we can also copy the improved comment from the Linux
kernel.
Fixes: 8ae51b6f324e ("net: ravb: Add Renesas Ethernet RAVB driver")
Signed-off-by: Paul Barker <[email protected]>
Signed-off-by: Marek Vasut <[email protected]> # Fix comment
Reviewed-by: Marek Vasut <[email protected]>
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The Renesas RAVB driver always requires bitbang MDIO bus support.
Fixes: 8ae51b6f324e ("net: ravb: Add Renesas Ethernet RAVB driver")
Signed-off-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Following on from commit 9a699a0a0d62 ("clk: rzg2l: Ignore enable for
core clocks"), we also need to ignore attempts to disable core clocks to
avoid the need for conditionals around clk_disable_bulk() calls in
drivers which support both RZ/G2L and other Renesas SoCs.
Signed-off-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Inline mdio_init() back into mdio_alloc(), separate
access to mdio_init() is no longer necessary.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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These functions are no longer necessary, remove them.
The struct bb_miiphy_bus is no longer necessary either,
remove it as well.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Use mdio_alloc() again to allocate MDIO bus. This is possible
because all the miiphybb parameters and ops passing is handled in
at bb_miiphy_read()/bb_miiphy_write() level.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Use mdio_alloc() again to allocate MDIO bus. This is possible
because all the miiphybb parameters and ops passing is handled in
at bb_miiphy_read()/bb_miiphy_write() level.
This also fixes previously missed bb_miiphy_free() in .remove
callback of this driver. which does not pose a problem anymore.
Fixes: 08eefb5e792d ("net: sh_eth: Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacks")
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Use mdio_alloc() again to allocate MDIO bus. This is possible
because all the miiphybb parameters and ops passing is handled in
at bb_miiphy_read()/bb_miiphy_write() level.
This also fixes previously missed bb_miiphy_free() in .remove
callback of this driver. which does not pose a problem anymore.
Fixes: 079eaca6e7b4 ("net: ravb: Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacks")
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Use mdio_alloc() again to allocate MDIO bus. This is possible
because all the miiphybb parameters and ops passing is handled in
at bb_miiphy_read()/bb_miiphy_write() level.
This also fixes previously missed bb_miiphy_free() in .remove
callback of this driver. which does not pose a problem anymore.
Fixes: cbb69c2fafcc ("net: designware: Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacks")
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Remove the priv member from struct bb_miiphy_bus and its assignment
from drivers. This turns struct bb_miiphy_bus int struct mii_dev
wrapper, to be cleaned up next.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Access to MDIO bus private data can be provided by both
struct mii_dev .priv member and struct bb_miiphy_bus .priv
member, use the former directly and remove .priv from the
later. Drop unused bb_miiphy_getbus(). This removes any
dependency on struct bb_miiphy_bus from the miiphybb code,
except for helper functions which will be removed later.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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The access to struct bb_miiphy_bus_ops via ops pointer in
struct bb_miiphy_bus is not necessary with wrappers added
in previous patch. Pass the ops pointer directly to both
bb_miiphy_read() and bb_miiphy_write() functions.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Do not call bb_miiphy_read()/bb_miiphy_write() accessors directly
in drivers, instead call them through wrapper functions. Those are
meant to be used as function parameter adaptation layer between
struct mii_dev callback function parameters and what the miiphybb
does expect and will soon expect. This is a preparatory patch, no
functional change.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Move miiphybb operations into separate struct bb_miiphy_bus_ops
structure, add pointer to struct bb_miiphy_bus_ops into the base
struct bb_miiphy_bus and access the ops through this pointer in
miiphybb generic code. The variable reshuffling in miiphybb.c
cannot be easily avoided.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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The RZN1 symbol name is CONFIG_RZN1, there is no CONFIG_ARCH_RZN1.
Since RZN1 enables CONFIG_ARCH_RENESAS as well, remove the special
RZN1 entry from Makefile, the RZN1 pinctrl driver will still be
pulled in via CONFIG_ARCH_RENESAS.
Fixes: e4aea57fa773 ("pinctrl: renesas: add R906G032 driver")
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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The Renesas R-Car Gen3 Salvator-X(S) boards contain USB micro-B port
on which the USBHS controller is accessible. Enable the USBHS UDC
driver to make this port usable, enable UMS USB Mass Storage support
to make it possible to expose block devices as USB Mass Storage to
Host PC.
The USB VID/PID is picked from R-Car Series, 3rd Generation reference
manual Rev.2.00 chapter 19.2.8 USB download mode, and matches R-Car H3
BootROM USB download mode VID/PID.
Signed-off-by: Marek Vasut <[email protected]>
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Introduce a 3-second delay and an informational message during boot to
enhance user experience.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Introduce a 3-second delay and an informational message during boot to
enhance user experience.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Introduce a 3-second delay and an informational message during boot to
enhance user experience.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Introduce a 3-second delay and an informational message during boot to
enhance user experience.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Introduce a 3-second delay and an informational message during boot to
enhance user experience.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Introduce a 3-second delay and an informational message during boot to
enhance user experience.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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For the Tegra 2, similar to other Tegra SoC generations, 'bootph-all'
must be applied to both display controllers.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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While PLLD/D2 is the nominal parent clock, all derived clocks are generated
from its single output, plld_out0, which is PLLD/D2 divided by two. Direct
use of PLLD/D2 is absent in peripheral clock configurations. Therefore,
clock derivation formulas must take in account this division.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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