| Age | Commit message (Collapse) | Author |
|
Drop warnings in get_cpu_rev and changes the return value
(a u32 instead of char * is returned) of the function
to be coherent with other processors.
Signed-off-by: Stefano Babic <[email protected]>
CC: Detlev Zundel <[email protected]>
CC: Fabio Estevam <[email protected]>
|
|
Move the header file and definitions of ftsmc020
static memory control unit from a320 SoC folder to
"drivers/mtd" folder.
This change will let other SoC which also use ftsmc020
could share the same header file.
Signed-off-by: Macpaul Lin <[email protected]>
|
|
Removed boot_flash_* extern variables.
boot_flash_type was totally unused. The other ones were actually constants, so
they have been replaced with #defines in the board config files.
Signed-off-by: Luca Ceresoli <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Sandeep Paulraj <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
|
|
Signed-off-by: Tom Warren <[email protected]>
|
|
Signed-off-by: Tom Warren <[email protected]>
|
|
CONFIG_OMAP34XX must be checked for existence, not value.
Signed-off-by: Luca Ceresoli <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Sandeep Paulraj <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
|
|
Signed-off-by: Alexander Holler <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
|
|
Signed-off-by: Albert ARIBAUD <[email protected]>
|
|
Fix include path of timer fttmr010 in a320evb.
Signed-off-by: Macpaul Lin <[email protected]>
|
|
|
|
Add i2c support to aspenite board with Armada100 soc.
Acked-by: Heiko Schocher <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Signed-off-by: Lei Wen <[email protected]>
|
|
Add i2c support to dkb board with pantheon soc.
Acked-by: Heiko Schocher <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Signed-off-by: Lei Wen <[email protected]>
|
|
Add i2c_clk_enable in the cpu specific code, since previous platform it,
while new platform don't need. In the pantheon and armada100 platform,
this function is defined as NULL one.
Acked-by: Heiko Schocher <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Signed-off-by: Lei Wen <[email protected]>
|
|
For better sharing with other platform other than pxa's,
it is more convenient to put the driver to the common place.
Acked-by: Heiko Schocher <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Signed-off-by: Lei Wen <[email protected]>
|
|
ftpmu010 related code has been moved to drivers/power/.
Signed-off-by: Po-Yu Chuang <[email protected]>
Signed-off-by: Albert Aribaud <[email protected]>
|
|
factor out boot cause function to common code to avoid
the duplicate code in each board support package
Signed-off-by: Jason Liu <[email protected]>
|
|
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Detlev Zundel <[email protected]>
|
|
Use the same method of the Linux kernel to print the MX31 silicon version on
boot.
Tested on a MX31PDK with a 2.0 silicon, where it shows:
CPU: Freescale i.MX31 rev 2.0 at 531 MHz
Signed-off-by: Fabio Estevam <[email protected]>
|
|
As exception among the i.MX processors, the i.MX31 has headers
without general names (mx31-regs.h, mx31.h instead of imx-regs.h and
clock.h). This requires several nasty #ifdef in the drivers to
include the correct header. The patch cleans up the driver and
renames the header files as for the other i.MX processors.
Signed-off-by: Stefano Babic <[email protected]>
|
|
Signed-off-by: Fabio Estevam <[email protected]>
|
|
The patch add CONFIG_HW_WATCHDOG to be used
with the internal watchdog timer of the MX31
processor. Two function are exported for the
board maintainers:
mxc_hw_watchdog_enable
mxc_hw_watchdog_reset
The board maintainer can decide to use mxc_hw_watchdog_reset as
hw_watchdog_reset, or to implement his own function to reset
the watchdog.
The watchdog timer can be configured with CONFIG_SYS_WD_TIMER_SECS
(value in seconds). The MX31 allows values between 0.5
(CONFIG_SYS_WD_TIMER_SECS = 0) and 128 seconds.
Signed-off-by: Stefano Babic <[email protected]>
|
|
Signed-off-by: Lo�c Minier <[email protected]>
|
|
Use the global data instead of bss variable, replace as follow.
count_value -> removed
timestamp -> tbl
lastdec -> lastinc
Signed-off-by: Minkyu Kang <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Acked-by: Albert ARIBAUD <[email protected]>
|
|
Use pwm functions for timer that is PWM timer 4.
Signed-off-by: Minkyu Kang <[email protected]>
|
|
This is common pwm driver of S5P.
Signed-off-by: Donghwa Lee <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Since nand boot have some limit for the first 4KB, We only
disable the LED function to reduce the code space. At the
same time, Fix the compile error for LED function undefined
in the compile time of nand_spl.
Signed-off-by: Zhong Hongbo <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Monitor protection region in FLASH did not cover .rel.dyn
and .dynsym sections, because it uses __bss_start to compute
monitor_flash_len. Use _end instead.
Add _end to linker scripts for end of u-boot image
Add _end_ofs to all the start.S.
Signed-off-by: Po-Yu Chuang <[email protected]>
|
|
Currently, _end is used for end of BSS section. We want _end to mean
end of u-boot image, so we rename _end to __bss_end__ first.
Signed-off-by: Po-Yu Chuang <[email protected]>
|
|
Signed-off-by: Fabio Estevam <[email protected]>
|
|
Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Magnus Lilja <[email protected]>
Tested-by: Magnus Lilja <[email protected]>
|
|
Pantheon Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref:
http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf
SoC versions Supported:
1) PANTHEON920 (TD)
2) PANTHEON910 (TTC)
Signed-off-by: Lei Wen <[email protected]>
|
|
Signed-off-by: Alexander Stein <[email protected]>
|
|
Signed-off-by: Tom Warren <[email protected]>
|
|
S5PC210 is a 32-bit RISC and Cortex-A9 Dual Core based micro-processor.
Signed-off-by: Minkyu Kang <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
|
|
Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss
values in the arm926ejs timers implementation.
The usage of bss values in drivers before initialisation of bss is forbidden.
In that special case some data in .rel.dyn gets corrupted.
This patch is similiar to the patch Dirk Behme posted
for the armv7/omap-common/timer.c and added suggestions
from Reinhard Meyer.
Tested on the arm926ejs mx27 based magnesium board
Tested on the arm926ejs kirkwood based suen3 board
Signed-off-by: Heiko Schocher <[email protected]>
cc: Albert ARIBAUD <[email protected]>
cc: Prafulla Wadaskar <[email protected]>
cc: Stefano Babic <[email protected]>
cc: Reinhard Meyer <[email protected]>
|
|
* remove LED initialization in front of relocation and bss init
Signed-off-by: Jens Scharsig <[email protected]>
|
|
Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss
values in the arm1136 timer driver for mx31 and omap24xx
The usage of bss values in drivers before initialisation of bss is forbidden.
In that special case some data in .rel.dyn gets corrupted.
This patch is similiar to the patch Dirk Behme posted
for the armv7/omap-common/timer.c
Tested on the mx31 based qong board
Signed-off-by: Heiko Schocher <[email protected]>
cc: Albert ARIBAUD <[email protected]>
Acked-by: Albert ARIBAUD <[email protected]>
|
|
Remove the useless code from start.S
Signed-off-by: Jason Liu <[email protected]>
Tested-by: Andreas Bießmann <[email protected]>
|
|
Because of the bss area is cleared after relocation, we've lost pointers.
This patch fixed it.
Signed-off-by: Minkyu Kang <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
|
|
The option CONFIG_SOC_DM6447 seems to have ended up
in the code by mistake. It is not used anywhere and
there is no chip called DM6447.
Signed-off-by: Sandeep Paulraj <[email protected]>
|
|
This commit fixes build errors on the DM6467 port.
Signed-off-by: Sandeep Paulraj <[email protected]>
|
|
Added arch/arm/cpu/arm926ejs/davinci/et1011c.c for handling
ET1011C gigabit phy. which overrides get_link_speed function
from default implementation. This enables output of 125 MHz
reference clock on SYS_CLK pin.
Signed-off-by: Prakash PM <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
|
|
The usage of bss values in drivers before initialisation of bss is forbidden.
In that special case some data in .rel.dyn gets corrupted.
This patch is the same as recently applied for arm926js architecture.
Signed-off-by: Stefano Babic <[email protected]>
CC: Heiko Schocher <[email protected]>
|
|
The patch adds basic support for the Freescale's i.MX35
(arm1136 based) processor.
The patch adds also a prototype for the initialization
of the FEC(ethernet controller) to netdev.h to avoid
warnings.
Signed-off-by: Stefano Babic <[email protected]>
|
|
Add initial support for Freescale MX53 processor,
- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro
Signed-off-by: Jason Liu <[email protected]>
|
|
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.
Signed-off-by: Mike Frysinger <[email protected]>
|
|
|
|
It can be optimised out by the compiler otherwise resulting
in obscure errors like a board not booting.
This has been documented in README since 2006 when these were
first fixed up for GCC 4.x.
Signed-off-by: John Rigby <[email protected]>
Fix some additional places.
Signed-off-by: Wolfgang Denk <[email protected]>
Acked-By: Albert ARIBAUD <[email protected]>
|
|
ARMADA 100 Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref: http://www.marvell.com/products/processors/applications/armada_100
SoC versions Supported:
1) ARMADA168/88AP168 (Aspen P)
2) ARMADA166/88AP166 (Aspen M)
3) ARMADA162/88AP162 (Aspen L)
Contributors:
Eric Miao <[email protected]>
Lei Wen <[email protected]>
Mahavir Jain <[email protected]>
Signed-off-by: Mahavir Jain <[email protected]>
Signed-off-by: Prafulla Wadaskar <[email protected]>
|
|
Make code build with older tool chains.
Signed-off-by: Wolfgang Denk <[email protected]>
|