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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191009
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Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/595148532
- MX6UL / ULZ
- Toradex board
- Allow to set OCRAM for MX6Q/D
- MX7ULP
- MX8: (container image, imx8mq_mek), SCU API
- fix several board booting from SD/EMMC (cubox-i for example)
- pico boards
[trini: display5 merged manually]
Signed-off-by: Tom Rini <[email protected]>
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- Move WATCHDOG_TIMEOUT_MSECS to Kconfig (Heiko)
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Pass spl_image and bootdev to board_return_bootrom.
i.MX8MN needs the args to let ROM to load images
Cc: Simon Glass <[email protected]>
Cc: Philipp Tomsich <[email protected]>
Cc: Kever Yang <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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At present this is defined in Kconfig but there is a separate one in the
CONFIG whitelist. It looks like these are duplicates.
Rename the non-Kconfig one and remove it from the whitelist.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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move WATCHDOG_TIMEOUT_MSECS to Kconfig and fix
all board defconfigs.
Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Lukasz Majewski <[email protected]>
Acked-by: Martyn Welch <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2
Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes
protocal support")
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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The correct config entry is CONFIG_PCIE_LAYERSCAPE and this
typo results in skipping the fixup of Linux PCIe DT nodes.
Also enable the fixup when Layerscape Gen4 controller driver
is enabled.
Fixes: 4da0e52c9dc0 (armv8: fsl-layerscape: fix config dependency
for layerscape pci code)
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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By default, i2c input clock is programmed at
platform clk / 2 in u-boot, but this is not
correct for all the platforms,
Update I2C clock divider's default values as per
SoC (LS1012A, LS1028A, LX2160A and LS1088A).
Signed-off-by: Chuanhua Han <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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The SP805-WDT module on LS1028A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.
Signed-off-by: Thomas Schaefer <[email protected]>
Signed-off-by: Zhao Qiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add esdhc peripheral clock support
for NXP layerscape platforms: LS1046ARDB, LS1043ARDB,
LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB
Signed-off-by: Yinbo Zhu <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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Create drivers/net/fsl-mc/Kconfig and move fsl-mc specific configs
from arch/arm/cpu/armv8/fsl-layerscape/Kconfig to this new Kconfig
Signed-off-by: Florinel Iordache <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, edma, qdma, gpu, display and sec.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Horia Geantă <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Horia Geantă <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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The current implementation assumes that the registers holding the ICIDs
are universally big endian. That's no longer the case on newer
platforms so update the code to take into account the endianness of
each register.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Horia Geantă <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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By default, i2c input clock is platform clk / 2, but some of the
platform of i2c clock divider does not meet this kind of circumstance,
so alone to set default values for these platforms.
Signed-off-by: Chuanhua Han <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Enable related configs on all ls1088aqds boards to support pcf2127
rtc DM function.
Signed-off-by: Chuanhua Han <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Enable related configs on all ls2088aqds boards to support ds3231
rtc DM function.
Signed-off-by: Chuanhua Han <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Enable related configs on all ls1028aqds boards to support pcf2127
rtc DM function.
Signed-off-by: Chuanhua Han <[email protected]>
Reviewed-by: Alex Marginean <[email protected]>
Tested-by: Alex Marginean <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Enable related configs on all lx2160ardb boards to support pcf2127
rtc DM feature.
Also remove SYS_I2C_MXC_I2Cx, where x is from 1 to 8 from
Kconfig.
Signed-off-by: Chuanhua Han <[email protected]>
Signed-off-by: Biwen Li <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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This file contains lots of internal details about the environment. Most
code can include env.h instead, calling the functions there as needed.
Rename this file and add a comment at the top to indicate its internal
nature.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
[trini: Fixup apalis-tk1.c]
Signed-off-by: Tom Rini <[email protected]>
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This header file is now only used by files that access internal
environment features. Drop it from various places where it is not needed.
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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Move env_set() over to the new header file.
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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Move env_init() over to the new header file.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Move this function over to the new header file.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Now that we have added driver model support to the TSEC driver,
convert ls1021atwr board to use it.
This depends on previous DM series for ls1021atwr:
http://patchwork.ozlabs.org/patch/561855/
Signed-off-by: Bin Meng <[email protected]>
Signed-off-by: Vladimir Oltean <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
[Vladimir] Made the following changes:
- Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi
- Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 -
a mistake ported over from Linux. Each SGMII PCS lies on the private
MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS).
- Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs
- Completely removed non-DM_ETH support from ls1021atwr
- Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio"
and from "fsl,tsec" to "fsl,etsec2" to match Linux
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This patch solves the following warnings:
arch/arm/mach-stm32mp/psci.c:
warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes]
Signed-off-by: Patrick Delaunay <[email protected]>
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Currently, CONFIG_TFABOOT is located in armv8/fsl-layerscape Kconfig,
but it will be also useful for other targets if some additional
configuration are necessary.
So move it to arch/arm/Kconfig.
Please note that CONFIG_TFABOOT still depends on
CONFIG_ARCH_SUPPORT_TFABOOT and so the menu won't come up
if any target doesn't need its own customization for TF-A boot.
This will maintain the compatibility.
Signed-off-by: AKASHI Takahiro <[email protected]>
Cc: Rajesh Bhagat <[email protected]>
Cc: York Sun <[email protected]>
Cc: Prabhakar Kushwaha <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Sriram Dash <[email protected]>
Cc: Hou Zhiqiang <[email protected]>
Cc: Peng Ma <[email protected]>
Cc: Yuantian Tang <[email protected]>
Cc: Pankit Garg <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier
UniPhier SoC updates for v2019.10
- import DT updates from Linux
- add UniPhier SPI controller driver
- make U-Boot image for 64bit SoCs position independent
- tidy up various init code for next generation SoCs
- misc cleanups
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Overload the weak function board_boot_order() so that besides choosing
the main boot device, we can fallback on USB boot by returning in the
BootROM, eg. if the NOR flash is empty while it was the primary boot
medium.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The _main call is not supposed to return at all: don't link the
branch.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Implement the weak board_return_to_bootrom() function so that when
enabling the spl_bootrom.c driver, one can make use of usbboot on
spear platforms. All necessary information to return to the BootROM
are stored in the BootROM's stack. The SPL stack pointer is reset so
we save the BootROM's stack pointer into the SPL .data section.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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There is no reason to do the few spear-related initialization, in a
different procedure than 'reset'. Spare one branching and get a linear
code flow by removing this indirection.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The link register is stored in R14. ARM assembly code allows to use
the 'lr' name to reference it instead of 'r14' which is not very
meaningful. Do the substitution to ease the reading.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Quoting ARM "RealView Compilation Tools Assembler Guide v4.0":
PUSH and POP are synonyms for STMDB and LDM (or LDMIA), with
the base register sp (r13), and the adjusted address written
back to the base register.
PUSH and POP are the preferred mnemonic in these cases.
Let's follow this recommandation to ease the reading and substitute
LDMIA/STMDB operations with PUSH/POP mnemonics.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Before cleaning a bit further the spear/start.S file, apply a few
cosmetic changes: capital letters, comment indentation and small
rewriting.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This comment describes the board state at the moment where we enter
the SPL. The description is entirely wrong; re-write it to fit the
reality.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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SPL BSS lies in SRAM and is actually initialized to 0 by the SPL in
arch/arm/lib/crt0.S:_main(), which is called by cpu_init_crit.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Rename Xloader as SPL in comments.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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It is clearly stated that board_init_f should *not* call
board_init_r. Indeed, board_init_f should return. The code will
continue through arch/arm/lib/crt0.S which will do more setup before
calling board_init_r.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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By default, CONFIG_SYS_INIT_SP_BSS_OFFSET was made invisible by not
giving a prompt to it.
The only way to define it is to hard-code an extra entry in SoC/board
Kconfig, like arch/arm/mach-tegra/tegra{186,210}/Kconfig.
Add a prompt to it in order to allow defconfig files to specify the
value of CONFIG_SYS_INIT_SP_BSS_OFFSET.
With this, CONFIG_SYS_INIT_SP_BSS_OFFSET would become always visible.
So, we need a new bool option to turn it off by default.
I move the 'default 524288' to the common place. This value is not too
big, but is big enough to avoid the overwrap of DT in most platforms.
If 512KB is not a suitable choice for your platform, you can change it
from your defconfig or menuconfig etc.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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Converted to use fsl_esdhc_imx for i.MX platforms.
Signed-off-by: Yangbo Lu <[email protected]>
Tested-by: Steffen Dirkwinkel <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Lukasz Majewski <[email protected]>
Reviewed-by: Martyn Welch <[email protected]>
Acked-by: Jason Liu <[email protected]>
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Fixes: 8163faf952 ARMv8: add optional Linux kernel image header
Signed-off-by: Mian Yousaf Kaukab <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Tested-by: Andreas Färber <[email protected]>
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LS1046AFRWY board supports LS1046A family SoCs. This patch
add base support for this board.
Board support's 4GB ddr memory, i2c, micro-click module,microSD card,
serial console,qspi nor flash,ifc nand flash,qsgmii network interface,
usb 3.0 and serdes interface to support two x1gen3 pcie interface.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Madalin Bucur <[email protected]>
Signed-off-by: Pankit Garg <[email protected]>
Signed-off-by: Pramod Kumar <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: Vabhav Sharma <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Layerscape began to use two eSDHC controllers, for example,
LS1012A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.
Signed-off-by: Yinbo Zhu <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Signed-off-by: Maciej Pijanowski <[email protected]>
Cc: [email protected]
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on
lane D and lane C respectively for 0x3363 protocol.
So fix serdes1 settings for ls1046a.
Signed-off-by: Maciej Pijanowski <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Fixes a link error on layerscape platform, linking fails with CONFIG_PCI
set and CONFIG_PCI_LAYERSCAPE unset.
Signed-off-by: Alex Marginean <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Change bootcmd update logic when CONFIG_ENV_ADDR is not defined
Signed-off-by: Pankit Garg <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Update qspi clock configuration in TFABOOT in case
of all boot sources except qspi boot source.
Signed-off-by: Pankit Garg <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Flushing L3 cache may need variable time depending upon cache line
allocation.
Coming up with a proper timeout value would be best handled by
simulations under multiple scenarios in your actual system.
>From the purely HN-F point of view, the flush would take ~15 cycles for
a clean line, and ~22 cycles for a dirty line. For the dirty line case,
there are many variables outside the HN-F that will increase the
duration per line. For example, a *DBIDResp from the SN-F/SBSX,
memory controller latency, SN-F/SBSX RetryAck responses, CCN ring
congestion, CCN ring hops, etc, etc. The worst-case timeout would
have to factor in all of these variables plus the HN-F cycles for
every line in the L3, and assuming all lines are dirty
In case if L3 is not flushed properly, system behaviour will be
erratic, so remove timeout and add loop to check status of L3 cache.
System will stuck in while loop if there is some issue in L3 cache
flushing.
Signed-off-by: Udit Kumar <[email protected]>
Signed-off-by: Meenakshi Aggarwal <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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