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Fix:
npe.c: In function 'npe_initialize':
npe.c:630:13: warning: assignment from incompatible pointer type
Signed-off-by: Anatolij Gustschin <[email protected]>
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In warm reset conditions on OMAP36xx/AM/DM37xx the rom code
incorrectly sets the DPLL4 clock input divider to /6.5 which
is an invalid value unless the input clock is 13MHz. When a JTAG
emulator is attached, a warm reset is necessary after the emulator
gains control of the process. This results in a loss of serial
output due to the invalid DPLL4 settings.
This patch fixes the issue by resetting the DPLL4 clock input
divider to /1 when the input clock is not 13MHz. AM/DM37x TRM
section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only
used when the input clock is 13MHz.
Signed-off-by: Matt Porter <[email protected]>
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Booting up these cores (dsp / ivahd / cortex-m3) is bad without
firmware running on them, and they will hang preventing any kind
of sleep transitions later on with the kernel.
Signed-off-by: Tero Kristo <[email protected]>
Acked-by: R Sricharan <[email protected]>
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If this is done in the bootloader, the FS-USB will later be stuck into
intransition state, which will prevent the device from entering idle.
Signed-off-by: Tero Kristo <[email protected]>
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This is needed for upcoming Toradex Colibri T20 upstream support.
Signed-off-by: Lucas Stach <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Add funcmux support for the default keyboard mapping.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Save SDRAM parameters into the warmboot scratch registers
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Yen Lin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Add code to set up the warm boot area in the Tegra CPU ready for a
resume after suspend.
Signed-off-by: Yen Lin <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Power supplies must be adjusted in line with clock frequency. This code
provides a simple routine to set the voltage to allow operation at maximum
frequency.
- Split PMU code into separate TPS6586X driver
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Add support for setting up the memory controller parameters. Boards
can set up an appropriate table in the device tree.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Provides an interface to aes.c for the warmboot code.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Yen Lin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass()
to find out if the Oscillator is bypassed. These are needed by warmboot.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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We want to include this from board code, so move the header into
an easily-accessible location.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This macro is generally useful to make it available in common.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Acked-by: Tom Rini <[email protected]>
Acked-by: Mike Frysinger <[email protected]>
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Do not define serial_putc() and serial_puts() calls if
CONFIG_SPL_SERIAL_SUPPORT is set.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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This code is part of battery boot support for i.MX28.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF
data pins interferes with the BootROM's boot mode sampling. So shut the
controller down.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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This patch implements code that samples i.MX28 boot pads and reports boot mode
accordingly.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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Pass memory size from SPL via structure located in SRAM instead of SCRATCH
registers. This allows passing more data about boot from SPL to U-Boot, like the
boot mode pads configuration.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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This solves issues when larger amount of DRAM is used, like 256MB.
Behave the same in case of CPU bypass as we do in case of EMI
bypass, but wait 15 ms. We need to wait until the clock domain
stabilizes.
This issue seemed to have been caused by not waiting after frobbing
with the CPU bypass, it was unrelated to memory, but had a direct
impact, causing trouble. This was yet another X-File of the
imx-bootlets, sigh. The conclusion is, trying a semi-random delay
(there is delay after the EMI bypass change), the issue is fixed.
Another possible explanation is that we do not do the "simple memory
test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of
the memory, while also outputing something on the serial port). This
might have caused the similar delay in the imx-bootlets and therefore
they didn't need to add this explicitly.
For now, this seems good fix enough, but to me, whole that memory
init code in imx-bootlets is completely flunked and it'd need deeper
investigation.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Acked-by: Detlev Zundel <[email protected]>
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Signed-off-by: Timo Ketola <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's
implement get_clocks function. This is how it seems to be implemented
elsewhere.
Signed-off-by: Timo Ketola <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Signed-off-by: Eric Nelson <[email protected]>
Signed-off-by: Stefano Babic <[email protected]>
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Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.
Note: This should be but can't be done in the DCD. The bootloader
prevents access to the ANATOP registers.
Signed-off-by: Dirk Behme <[email protected]>
CC: Jason Chen <[email protected]>
CC: Jason Liu <[email protected]>
CC: Ranjani Vaidyanathan <[email protected]>
CC: Stefano Babic <[email protected]>
CC: Fabio Estevam <[email protected]>
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This reverts commit 69d26d09de1cb93e0a09ca71d9f0d41a66f0756a.
Apparently, this commit got mainline only because of out-of-tree
port and causes breakage on board that is mainline. Revert.
Reason:
* The OOT board has 512MB of DRAM, enabling this additional address
line enabled it to work fine with 512MB of RAM.
* Every mainline port has max. 256MB of DRAM, therefore this revert
has no impact on any mainline port
* Though this caused a problem with new M28 board with 256MB of DRAM
where the chips are wired differently. The patch-to-be-reverted
caused the DRAM to behave like this:
[128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again]
Therefore to retain the current one-memory-init-rules-them-all situation,
revert this patch until another board emerges and will actually be pushed
mainline that needs different setup.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
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Print CPU information within board_late_init().
This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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mx5: Add clock config interface
Add clock config interface support, so that we
can configure CPU or DDR clock in the later init
Signed-off-by: Jason Liu <[email protected]>
Signed-off-by: Eric Miao <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
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get_ahb_clk() is a common function between mx5 and mx6.
Place it into imx-common directory.
Cc: Dirk Behme <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
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The MX53 SATA interface can use an internal clock (USB PHY1)
instead of an external clock. This is an undocumented feature, but used
on most Freescale's evaluation boards, such as MX53-loco.
As stated by Freescale's support:
Fuses (but not pins) may be used to configure SATA clocks.
Particularly the i.MX53 Fuse_Map contains the next information
about configuring SATA clocks :
SATA_ALT_REF_CLK[1:0] (offset 0x180C)
'00' - 100MHz (External)
'01' - 50MHz (External)
'10' - 120MHz, internal (USB PHY)
'11' - Reserved
Signed-off-by: Stefano Babic <[email protected]>
CC: Fabio Estevam <[email protected]>
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Add base address and MXC_SATA_CLK to return
the clock used for the SATA controller.
Signed-off-by: Stefano Babic <[email protected]>
CC: Fabio Estevam <[email protected]>
CC: Dirk Behme <[email protected]>
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To sets up lcd and mipi clock in EXYNOS display driver, added clock interface.
Signed-off-by: Donghwa Lee <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Inki Dae <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This is definitions of system registers and power mananagement registers for EXYNOS SoC.
Signed-off-by: Donghwa Lee <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Inki Dae <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Introduce a __weak misc_init_r function that just runs dieid_num_r().
Remove misc_init_r from cm_t35, mcx, omap3_logic and mt_ventoux as this was
all they did for misc_init_r.
Cc: Igor Grinberg <[email protected]>
Cc: Ilya Yanok <[email protected]>
Cc: Peter Barada <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Acked-by: Igor Grinberg <[email protected]>
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OMAP4/5 had an empty arch_cpu_init() so drop that along with
CONFIG_ARCH_CPU_INIT
Signed-off-by: Tom Rini <[email protected]>
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Enable -march=armv7-a for armv7 platforms if the tool-chain
supports it. This in turn results in Thumb-2 code generated
for these platforms if CONFIG_SYS_THUMB_BUILD is enabled.
Signed-off-by: Aneesh V <[email protected]>
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Use ENTRY and ENDPROC with assembly functions to ensure
necessary assembler directives for all functions.
Signed-off-by: Aneesh V <[email protected]>
Acked-by: Mike Frysinger <[email protected]>
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Warm reset is not functional in case of omap5430ES1.0.
So override the weak reset_cpu function to use
cold reset instead.
Signed-off-by: R Sricharan <[email protected]>
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The reset.S has the function to do a warm reset on OMAP
based socs. Moving this to a reset.c file so that this
acts a common layer to add any reset related functionality
for the future.
Signed-off-by: R Sricharan <[email protected]>
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In OMAP5 Boot device mode of 6 and 7 should be mapped to mmc2/eMMC
Signed-off-by: Balaji T K <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The ddr part name used in OMAP5 ES1.0 soc is a SAMSUNG part and
not a ELPIDA part. So change this.
Signed-off-by: R Sricharan <[email protected]>
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Add support to identify the device as GP/EMU/HS.
Signed-off-by: R Sricharan <[email protected]>
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Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
include all the registers and not simply the io regs.
Signed-off-by: R Sricharan <[email protected]>
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The different silicon revision variable names was defined for OMAP4 and
OMAP5 socs. Making the variable common so that some code can be
made generic.
Signed-off-by: R Sricharan <[email protected]>
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The break statement is missing in init_omap_revision function, resulting
in a wrong revision identification. So fixing this.
Signed-off-by: R Sricharan <[email protected]>
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The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.
Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
http://lists.denx.de/pipermail/u-boot/2012-March/119151.html
Signed-off-by: R Sricharan <[email protected]>
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The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.
Signed-off-by: R Sricharan <[email protected]>
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The control module provides options to set various signal
integrity parameters like the output impedance, slew rate,
load capacitance for different pad groups. Configure these
as required for the omap5430 sevm board.
Signed-off-by: R Sricharan <[email protected]>
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