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This commit allows to build Panasonic UniPhier family:
PH1-LD4, PH1-Pro4, PH1-sLD8
Signed-off-by: Masahiro Yamada <[email protected]>
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These are used by Panasonic UniPhier SoC family.
Signed-off-by: Masahiro Yamada <[email protected]>
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Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Arnab Basu <[email protected]>
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This commit moves:
CONFIG_OF_CONTROL
CONFIG_OF_SEPARATE
CONFIG_OF_EMBED
CONFIG_OF_HOSTFILE
Because these options are currently not supported for SPL,
the "Device Tree Control" menu does not appear in the SPL
configuration.
Note:
zynq-common.h should be adjusted so as not to change the
default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Minkyu Kang <[email protected]>
Acked-by: Michal Simek <[email protected]>
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The macro MIN, MAX is defined as the aliase of min, max,
respectively.
Signed-off-by: Masahiro Yamada <[email protected]>
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When use pcr (peripheral control register), then we won't need
to care about the peripheral ID.
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.
Signed-off-by: Murali Karicheri <[email protected]>
Signed-off-by: Keegan Garcia <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.
We can delete the ones in arch and board Kconfig files.
This commit can be easily reproduced by the following command:
find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
N
s/\n[[:space:]]*string//
}
'
Signed-off-by: Masahiro Yamada <[email protected]>
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Commit 224beb833e544b802f08765271cec07667d39669 add clock
enabling function for FEC, but the masks are not available
for SX processor and the mx6sxsabresd cannot be built clean.
Signed-off-by: Stefano Babic <[email protected]>
CC: Fabio Estevam <[email protected]>
CC: Nikita Kiryanov <[email protected]>
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Let PCI on mx6solox also be supported.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Signed-off-by: Nikolay Dimitrov <[email protected]>
Cc: Stefano Babic <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
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The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.
But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.
Signed-off-by: Ye.Li <[email protected]>
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Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.
This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware of the way the calculation
is performed.
Refactor the calculation.
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).
Configure MMDC for slow pd.
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Cc: Igor Grinberg <[email protected]>
Acked-by: Igor Grinberg <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
Acked-by: Tim Harvey <[email protected]>
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Bit 16 in mapsr register is in a reserved field. Don't write to it.
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Acked-by: Tim Harvey <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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No functional changes.
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Acked-by: Tim Harvey <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.
Cc: Stefano Babic <[email protected]>
Cc: Igor Grinberg <[email protected]>
Acked-by: Igor Grinberg <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: Jason Jin <[email protected]>
Signed-off-by: Jingchang Lu <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
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Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This config is valid for two devices:
- Odroid X2,
- Odroid U3.
Signed-off-by: Przemyslaw Marczak <[email protected]>
Cc: Minkyu Kang <[email protected]>
Cc: Tom Rini <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch introduces code clean-up for exynos boot mode check.
It includes:
- removal of typedef: boot_mode
- move the boot mode enum to arch-exynos/power.h
- add bootmode for sequence: eMMC 4.4 ch4 / SD ch2
- add new function: get_boot_mode() for OM[5:1] pin check
- update spl boot code
Signed-off-by: Przemyslaw Marczak <[email protected]>
Changes v5:
- exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2)
Changes v6:
- none
changes v7:
- change boot mode name: BOOT_MODE_MMC to BOOT_MODE_SD
Signed-off-by: Minkyu Kang <[email protected]>
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This change fixes the bad gpio configuration for the exynos dwmmc.
Signed-off-by: Przemyslaw Marczak <[email protected]>
Cc: Beomho Seo <[email protected]>
Cc: Minkyu Kang <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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On DRA72x, EMIF supports DDR3 upto 667MHz.
Adding the required settings for DDR3 at 666MHz and enabling it.
Signed-off-by: R Sricharan <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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There is no reason to redefine pure readl/writel functions.
So remove this redundancy.
Signed-off-by: Ivan Khoronzhuk <[email protected]>
Acked-by: Vitaly Andrianov <[email protected]>
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The mask for BWADJ field of PASSPLLCTL0 register has to be 0xff, but
by mistake, here is used shift instead of mask, so correct it.
Signed-off-by: Ivan Khoronzhuk <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the Nomadik board select menu to nomadik/Kconfig.
Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="nomadik").
Signed-off-by: Masahiro Yamada <[email protected]>
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Move Highbank-specific settings to highbank/Kconfig.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Rob Herring <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the Orion5x board select menu to orion5x/Kconfig.
Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="orion5x").
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the Keystone board select menu to keystone/Kconfig.
Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="keystone").
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Cc: Vitaly Andrianov <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP5 board select menu to omap5/Kconfig.
Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap5").
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Cc: Lokesh Vutla <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP4 board select menu to omap4/Kconfig.
Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap4").
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Cc: Lokesh Vutla <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP3 board select menu to omap3/Kconfig.
Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap3
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the Davinci board select menu to davinci/Kconfig.
Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="davinci").
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Sandeep Paulraj <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the Exynos board select menu to exynos/Kconfig.
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="exynos").
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Minkyu Kang <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the KirkWood board select menu to kirkwood/Kconfig.
Consolidate also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="kirkwood").
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Prafulla Wadasdkar <[email protected]>
Cc: Luka Perkov <[email protected]>
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Move Versatile-specific settings to versatile/Kconfig.
Signed-off-by: Masahiro Yamada <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the Rmobile board select menu to rmobile/Kconfig.
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="rmobile").
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the Tegra board select menu to tegra/Kconfig.
Insert the Tegra SoC select menu between the arch select and the
board select.
Architecture select
|-- Tegra Platform (Tegra)
|- Tegra SoC select (Tegra20 / 30 / 114 / 124)
|- Board select
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows:
config TEGRA
bool
select SPL
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Cc: Tom Warren <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the Zynq board select menu to zynq/Kconfig.
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="zynq").
Refactor board/xilinx/zynq/MAINTAINERS too.
Signed-off-by: Masahiro Yamada <[email protected]>
Tested-by: Michal Simek <[email protected]>
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Commit 41623c9 'arm: move exception handling out of start.S files' missed some
linker scripts. Hence, some boards no longer had exception handling linked since
this commit. Restore the original behavior by adding the .vectors section to
these linker scripts.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
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Base support for the Broadcom NSP SoC.
Based on iproc-common and the SoC specific reset function.
Signed-off-by: Scott Branden <[email protected]>
Signed-off-by: Steve Rae <[email protected]>
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Base support for the Broadcom Cygnus SoC.
Based on iproc-common and the SoC specific reset function.
Signed-off-by: Scott Branden <[email protected]>
Signed-off-by: Steve Rae <[email protected]>
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The iproc architecture code is present in several Broadcom
chip architectures, including Cygnus and NSP.
Signed-off-by: Scott Branden <[email protected]>
Signed-off-by: Steve Rae <[email protected]>
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