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Since we have new DRAM type and to support different DRAM size in different
CS, we need more bits, so introduce sys_reg3 to record the info.
Note that the info in sys_reg3 is extension to sys_reg2 and the info in
sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as
VERSION2.
All the ENC macro are moved to sdram_common.h since the sdram.c only
need to do the info decode.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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The sdram.h suppose to be helper file for sdram.c which including dram
size decode and some u-boot related dram init interface, and all
structure and function for dram driver move to sdram_common.h
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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rename sdram_common.c in arch/arm/mach-rockchip to sdram.c;
so that we can use the file name sdram_common.c in dram driver for
better understand the code;
clean the related file who has use the header file at the same time.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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The header file sdram.h is used for rk3288 and similar SoCs, rename it
to make it more understandable.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191105
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i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
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https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.
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- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
fsl-layerscape, pci, icid, PSCI
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Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.
Signed-off-by: Simon South <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Horia Geanta <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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LX2160A chips have 4 sata controllers. Add missing base addresses for
SATA3 and SATA4.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Horia Geanta <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below
compilation error appears
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function)
Fix it by wrapping with CONFIG_IS_ENABLED().
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Horia Geanta <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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Provide optimized memcpy_{from,to}io() and memset_io(). This is required
when moving large amount of data to and from IO regions such as IP
registers or accessing memory mapped flashes.
Code is borrowed from Linux Kernel v5.4.
Signed-off-by: Vignesh Raghavendra <[email protected]>
Reviewed-by: Lokesh Vutla <[email protected]>
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i.MX8MN support loading images with rom api, so we implement
reuse board_return_to_bootrom to let ROM loading images.
Signed-off-by: Peng Fan <[email protected]>
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Add pin header for i.MX8MN
Signed-off-by: Peng Fan <[email protected]>
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i.MX8MN does not have LVTTL, it has a PE property
Signed-off-by: Peng Fan <[email protected]>
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i.MX8MN has similar architecture with i.MX8MM, so it could reuse
the clock code of i.MX8MM, but i.MX8MN has different CCM root
configurations, so need a separate root entry.
Signed-off-by: Peng Fan <[email protected]>
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Add a dummy cpu type and support get_cpu_rev for i.MX8MN
Signed-off-by: Peng Fan <[email protected]>
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Add support for updating FCB/DBBT on i.MX7:
- additional new fields in FCB structure
- Leverage hardware BCH/randomizer for writing FCB
Signed-off-by: Igor Opaniuk <[email protected]>
Tested-by: Max Krummenacher <[email protected]>
Reviewed-by: Oleksandr Suvorov <[email protected]>
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Extend GPMI Integrated ECC Control Register Description, include
additional defines for enabling randomizer function and providing
proper randomizer type.
For additional details check i.MX7 APR, section
9.6.6.3 GPMI Integrated ECC Control Register Description
(GPMI_ECCCTRLn)
Signed-off-by: Igor Opaniuk <[email protected]>
Tested-by: Max Krummenacher <[email protected]>
Reviewed-by: Oleksandr Suvorov <[email protected]>
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Need to pass total 5 arguments for SIP HAB call on i.MX8MQ,
so update the interface to add new argument.
Signed-off-by: Ye Li <[email protected]>
[agust: fixed imx8m-power-domain build]
Signed-off-by: Anatolij Gustschin <[email protected]>
Reviewed-by: Patrick Wildt <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Add init_nand_clk to enable gpmi nand clock. Since i.MX8MQ not use CCF,
so we still use legacy mode to configure the clock.
Signed-off-by: Peng Fan <[email protected]>
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imx6_is_bmode_from_gpr9 always returns false, because
IMX6_SRC_GPR10_BMODE is 1<<28 and gets casted to u8 on return.
This moves the function body into imx6_src_get_boot_mode, since that is the
only one using it and it is on the same abstraction level (accessing
registers directly).
Signed-off-by: Claudius Heine <[email protected]>
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Introduce disable_ipu_clock(). This is done in preparation for
configuring the NoC registers on i.MX6QP in SPL.
Afer the NoC registers are set the IPU clocks can be disabled.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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The Allwinner H6 SoC has a register to set the PIO banks' voltage. When
it mismatches the real voltage supplied to the VCC to the PIO supply,
the PIO will work improperly.
The PIO controller also has a register that contains the status of each
VCC rail of the PIO supplies, and it has the same definition with the
configuration register. so we can just copy the content of this register
to the configuration register at startup, to ensure the configuration is
correct at startup stage.
Signed-off-by: Icenowy Zheng <[email protected]>
[jagan: s/__maybe__unused/__maybe_unused]
Signed-off-by: Jagan Teki <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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Half DQ configuration seems to be very rare for H6 based boards/STBs,
but exists nevertheless. Currently the only known product which needs
this support is Tanix TX6 mini.
This commit adds support for half DQ configuration. Code was tested
for regressions on other configurations (OrangePi 3 1 GiB/LPDDR3, Tanix
TX6 4 GiB/DDR3) and none were found.
Thanks to Icenowy Zheng for help with this code.
Reviewed-by: Andre Przywara <[email protected]>
Tested-by: thomas graichen <[email protected]>
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Maxime Ripard <[email protected]>
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LX2160A/LX2120A/LX2080A SVR value should be
0x873600/0x873620/0x873602
Previous values were valid only if CAN fuse is blown.
Signed-off-by: Wasim Khan <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a.
Both ls1027a and ls1017a personalities are lower functionality version
which doesn't support the multimedia subsystems, like LCD, GPU.
To disable multimedia feature on non-multimedia version,
set the status property to disabled in dts nodes.
Signed-off-by: Tang Yuantian <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and
SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write
snoop signal on LS1043A and LS1046A.
Signed-off-by: Ran Wang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Update SCFG_QSPI_CLKSEL value : 0xC -> 0x5
which means ClusterPLL/16
Signed-off-by: Ashish Kumar <[email protected]>
Signed-off-by: Kuldeep Singh <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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Add LS1027A, LS1018A and LS1017A personalities support to
LS1028A SoC family.
LS1028A is the prime personality of LS1028A SoC family.
LS1027A is a lower funtionality version of QorIQ LS1028A
which does not support the multimedia subsystems, such as LCD
controller, GPU, and eDP PHY.
The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72
core, low power versions of the QorIQ LS1028A and LS1027A
SoCs respectively.
Signed-off-by: Tang Yuantian <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191014
-------------------
Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628
- logicpd pinmux
- i.MX7ULP: imx_ddr_size
- fixes Toradex i.MX6/i.MX7
- pico-imx7d
- tpc70 converted to DM
- New Board: meerkat96
- add HAB version command
- i.MX8 :
imx8: Jump from alias to OCRAM address at SPL init
imx8qm/qxp: Set SPL TEXT base to OCRAM base
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https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- Add sdhci driver for Broadcom iProc platform
- Add a driver callback for power-cycle for mmc
- Implement host_power_cycle callback for stm32_sdmmc2
- spl: dm_mmc: Initialize only the required mmc device
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THe RVT data includes a major and minor version in its header
parameter. Add a new command to print this out.
Signed-off-by: Sjoerd Simons <[email protected]>
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When running SPL on iMX8, the A core starts at address 0
which is a alias to OCRAM 0x100000.
The alias only map first 96KB of OCRAM, so this require the
SPL size can't beyond 96KB. But when using SPL DM, the size increase
significantly and may exceed 96KB.
So to fix the problem, we will change SPL linker address to OCRAM
address 0x100000. And then jump to the absolute address not the PC relative
address for entering OCRAM.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Oleksandr Suvorov <[email protected]>
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readb is unconditionally defined earlier in io.h, so there's no point
checking whether it's undefined.
Signed-off-by: Rasmus Villemoes <[email protected]>
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No ARM board seems to define __mem_pci - and if it did, one would get tons of
./arch/arm/include/asm/io.h:307:0: warning: "readl" redefined
warnings, because readl and friends are unconditionally defined
earlier in io.h. Moreover, the redefinitions lack the memory barriers
that the first definitions have. So I'm guessing this is practically
dead code.
Signed-off-by: Rasmus Villemoes <[email protected]>
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Add SDHCI driver for iProc family of Broadcom devices.
Signed-off-by: Corneliu Doban <[email protected]>
Signed-off-by: Pramod Kumar <[email protected]>
Signed-off-by: Pavithra Ravi <[email protected]>
Signed-off-by: Bharat Kumar Reddy Gooty <[email protected]>
Signed-off-by: Vladimir Olovyannikov <[email protected]>
Signed-off-by: Arun Parameswaran <[email protected]>
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CONFIG_SECURE_BOOT is too generic and forbids to use it for cross
architecture purposes. If Secure Boot is required for imx, this means to
enable and use the HAB processor in the soc.
Signed-off-by: Stefano Babic <[email protected]>
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Add more scfw api for clk/partition/seco usage
The api will be used by ccf/partition/secure boot.
Signed-off-by: Peng Fan <[email protected]>
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Introduce clk implementation for i.MX8MM, including pll configuration,
ccm configuration. Mostly will be done clk dm driver,
but such as DRAM part, we still use non clk dm driver, because we
have limited sram.
Signed-off-by: Peng Fan <[email protected]>
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i.MX8MQ and i.MX8MM use different analog pll design, but they
share same ccm design.
Add clock_imx8mq.h for i.MX8MQ
keep common part in clock.h
Signed-off-by: Peng Fan <[email protected]>
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i.MX8MM does not have LVTTL, it has a PE property
Signed-off-by: Peng Fan <[email protected]>
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Add pin header file for i.MX8MM
To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be
selected.
Signed-off-by: Peng Fan <[email protected]>
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i.MX8MM has similar architecture with i.MX8MQ, but it has totally
different PLL design and register layout change.
Signed-off-by: Peng Fan <[email protected]>
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Drop unused register definitions and structures for i.MX8MQ
Signed-off-by: Peng Fan <[email protected]>
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Add i.MX8MM cpu type and related helper functions
Signed-off-by: Peng Fan <[email protected]>
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Add support for the power domain controller that's used on the
i.MX8MQ. This will be needed to be able to power on the PCIe
controller. Bindings taken from Linux, driver implementation
taken from the i.MX8 power domain controller and adjusted for
the i.MX8M SoC.
Signed-off-by: Patrick Wildt <[email protected]>
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Add sc_pm_is_partition_started to check whether a partition
has been started. This will be used to detect M4 partition booted up or
not, then we could choose which dtb to use. If M4 is up, we need
use dtb, such as imx8qm-mek-rpmsg.dtb.
Signed-off-by: Peng Fan <[email protected]>
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We use information from ATF to know whether OP-TEE is running or not.
So save args passed from ATF.
Signed-off-by: Peng Fan <[email protected]>
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