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The pad settings for DISP0_DATA02 and DISP0_DAT10 were not
set in the same way as DISP0_DAT00-23, causing much flicker
in parallel RGB displays on Dual-Lite and Solo processors.
These settings now match the i.MX6 Dual and Quad core versions.
Note that this fixes a regression in commit b47abc3 and that
this is the second time we've had a regression on these two
pads (See commit e654ddf).
Signed-off-by: Eric Nelson <[email protected]>
Acked-by: Otavio Salvador <[email protected]>
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Newer AM437x silicon requires us to explicitly power up
the USB2 PHY. By implementing usb_phy_power() we can
achieve that.
Signed-off-by: Felipe Balbi <[email protected]>
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* This is done by limiting the ARM's bandwidth and setting DSS priority in
the EMIF controller to ensure underflows do not occur.
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* Boot failures have been discovered due to a combination of routing issues and
non optimal ddr3 timings in the EMIF
* Since ddr3 timings are different after significant board layout changes
different timings are required for alpha, beta and production boards.
Signed-off-by: Franklin S. Cooper Jr <[email protected]>
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Fix following compilation error when CONFIG_ARM64 is defined
Error: unknown or missing system register name at operand 2
-- `mrs x0,daifmsr daifset,#3'
Signed-off-by: Shaibal.Dutta <[email protected]>
Signed-off-by: Darwin Rambo <[email protected]>
Reviewed-by: Darwin Rambo <[email protected]>
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cc: Tom Rini <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
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Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Wolfgang Denk <[email protected]>
CC: Pavel Machek <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
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To enable the DesignWare watchdog support at SOCFPGA
Cyclone V dev kit.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Tom Rini <[email protected]>
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This patch returns back support for old ep93xx processors family
Signed-off-by: Sergey Kostanbaev <[email protected]>
Cc: [email protected]
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This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.
cc: Albert Aribaud <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Support for GIC 500 (based on GICv3 arch)
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Arnab Basu <[email protected]>
Signed-off-by: J. German Rivera <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
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Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Varun Sethi <[email protected]>
Signed-off-by: Arnab Basu <[email protected]>
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Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun <[email protected]>
CC: David Feng <[email protected]>
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This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera <[email protected]>
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The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF
images and u-boot, and does this for virtual platforms by using
semihosting. This commit extends this idea by allowing u-boot to also
use semihosting to load the kernel/ramdisk/dtb. This eliminates the need
for a bootwrapper and produces a more realistic boot sequence with
virtual models.
Though the semihosting code is quite generic, support for armv7 in
fastmodel is less useful due to the wide range of available silicon
and the lack of a free armv7 fastmodel, so this change contains an
untested armv7 placeholder for the service trap opcode.
Please refer to doc/README.semihosting for a more detailed description
of semihosting and how it is used with the armv8 virtual platforms.
Signed-off-by: Darwin Rambo <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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I2C read transactions are typically implemented as follows:
START(write) address REPEATED_START(read) data... STOP
However, Tegra's I2C driver currently implements reads as follows:
START(write) address STOP START(read) data... STOP
This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Yen Lin <[email protected]>
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Conflicts:
boards.cfg
Conflict was trivial between goni maintainer change and
lager_nor removal.
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Support the iotrace feature for ARM, when enabled.
Signed-off-by: Simon Glass <[email protected]>
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Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF
definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h
Acked-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
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The definitions inside emif_defs.h concern davinci nand driver and
should be in it's header. So create header file for davinci nand
driver and move definitions from emif_defs.h and nand_defs.h to it.
Acked-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
[trini: Fixup more davinci breakage]
Signed-off-by: Tom Rini <[email protected]>
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According to:
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/log/?h=imx_v2009.08_3.0.35_4.1.0
ENGR00287268 mx6: fix the secure boot issue on the new tapout chip
commit 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b
newer i.MX6 silicon revisions have an updated ROM and HAB API table.
Please see also:
i.MX Applications Processors Documentation
Engineering Bulletins
EB803, i.MX 6Dual/6Quad Applications Processor Silicon Revsion 1.2 to 1.3 Comparison
With this change the secure boot status is correctly displayed
Signed-off-by: Stefano Babic <[email protected]>
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mx6 reference manual incorrectly states that the DEVICE_TYPE field of
IOMUXC_GPR12 register should be configured as '0010' for setting the PCI
controller in RC mode. The correct value should be '0100' instead.
This also aligns with the same value used in the mx6 pci kernel driver.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Sometimes Read DQ and DQS are not in phase. Since, this
phase shift differs from board to board, we need to
calibrate it at DRAM init phase, that's read DQ calibration.
This patch adds SW Read DQ calibration routine to compensate
this skew.
Signed-off-by: Alim Akhtar <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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mkconfig links ${objtree}/include/asm/proc/ to
${srctree}/arch/${arch}/include/asm/proc-armv/. This seems to be a
remnant from the past. Ever since its introduction in 2003 it is used
only in ARM build and always links to same place, so let's simplify
the code, remove it and reference directly where needed.
Successful MAKEALL for ARM and PowerPC verified on Linux.
Signed-off-by: Vasili Galka <[email protected]>
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Add QSPI support for VF610TWR, such as clock and iomux.
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: Chao Fu <[email protected]>
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Add PAD_CTL_DSE_150ohm and PAD_CTL_PUS_22K_UP for VF610 in
IOMUX_PAD structure.
Signed-off-by: Alison Wang <[email protected]>
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Similar to OMAP4/5 we need to scale the voltage up prior to changing the
clock frequencies up higher. Add a similar hook to start with.
Signed-off-by: Tom Rini <[email protected]>
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For usage of timer6 within B&R we need this defines to enable clock
modules and clk-source.
Also the 'Timer register bits' are expanded.
By the way we add defines for all timers within AM335x SoC.
Cc: [email protected]
Signed-off-by: Hannes Petermaier <[email protected]>
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Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.
Acked-By: Vitaly Andrianov <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
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GPMC_NAND_ECC_LP_x16_LAYOUT
OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.
Signed-off-by: Pekon Gupta <[email protected]>
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Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list
and add macros for declaring the pad_list that take into account the
SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL
iomux).
Cc: Stefan Roese <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Andy Ng <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Tapani Utriainen <[email protected]>
Cc: Tom Rini <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
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- add function for configuring iomux based on board-specific regs
- add function for configuring mmdc based on board-specific and
chip-specific data
Cc: Stefan Roese <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Andy Ng <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Tapani Utriainen <[email protected]>
Cc: Tom Rini <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
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Add memory-mapped structures for MMDC iomux and configuration. Note that whi
the MMDC configuration registers are common between the IMX6DQ
(IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) types the iomux
registers differ. This requires two sets of structures.
Add structures to describe DDR3 device information, system information
(memory layout, etc), and MMDC calibration registers that can be used to
configure the MMDC dynamically.
We define these structures for SPL builds instead of including mx6q-ddr.h an
mx6dl-ddr.h which use the same namespace and are only useful for imximage cf
files.
Cc: Stefan Roese <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Andy Ng <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Tapani Utriainen <[email protected]>
Cc: Tom Rini <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
Acked-by: Nikita Kiryanov <[email protected]>
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arch/arm/include/asm/spl.h requires all SoCs to have
arch/arm/include/asm/arch-*/spl.h.
But many of them just define BOOT_DEVICE_* macros.
Those macros are used in the "switch (boot_device) { ... }"
statement in common/spl/spl.c.
So they should not be archtecture specific, but be described as
a simpile enumeration.
This commit merges most of arch/arm/include/asm/arch-*/spl.h
into arch/arm/include/asm/spl.h.
With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h
will be merged, while I am not sure about OMAP and Exynos.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Andreas Bießmann <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Tom Warren <[email protected]>
CC: Stefano Babic <[email protected]>
CC: Minkyu Kang <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Acked-by: Andreas Bießmann <[email protected]>
Acked-by: Michal Simek <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Acked-by: Tim Harvey <[email protected]>
Tested-by: Bo Shen <[email protected]> [on sama5d3xek board for at91 part]
Acked-by: Stephen Warren <[email protected]>
Tested-by: Stefano Babic <[email protected]> [applying Tim's i.MX6 patches]
Acked-by: Tom Rini <[email protected]>
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Setting ps_hold ought to be one of the first things we do when we
first boot up. If we wait until the main u-boot runs we won't set it
in time and the PMIC may power us back off.
Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Signed-off-by: Josh Wu <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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The at91x40.h is not exist. So we remove it.
Signed-off-by: Josh Wu <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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If without switch to main crystal oscillator, the sama5d3 SoC will
use internal on chip RC oscillator.
In order to get better accuracy, switch to main crystal oscillator.
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote:
> > + case 1:
> > +#if CONFIG_MMC1_PG
> Are you sure that this is correct and shouldn't be:
>
> +#ifdef CONFIG_MMC1_PG
>
> ?
It's "correct" in so far as it works (the boards.cfg config stuff
#defines things to 1), but I think you are right that it isn't the
preferred style. But...
> A quick scan through this patch series shows that this define
> is not set at all. Perhaps its outdated? Or is it used to support
> some other sunxi SoC? Not sure, perhaps it should be removed for
> now.
...I had thought that it was to support some other board which wasn't
being upstreamed right now, so eventually useful and harmless for now,
but I've just checked and it isn't actually used by any of the boards in
u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it.
Rather than resend the entire series, here is v5.1 of this patch.
> Other than this please add my:
>
> Reviewed-by: Stefan Roese <[email protected]>
Thanks!
8<---------------------------------
>From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001
From: Ian Campbell <[email protected]>
Date: Fri, 7 Mar 2014 04:29:39 +0000
Subject: [PATCH v5.1 7/8] sunxi: mmc support
This adds support for the MMC controller on the Allwinner A20 (sun7i)
processor.
Signed-off-by: Henrik Nordstrom <[email protected]>
Signed-off-by: Luke Leighton <[email protected]>
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Wills Wang <[email protected]>
Signed-off-by: Ian Campbell <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Cc: Tom Cubie <[email protected]>
Cc: Aaron Maoye <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This patch adds generic board, start of day and basic build system support for
the Allwinner A20 (sun7i) processor. This code will not been compiled until the
build is hooked up in a later patch. It has been split out to keep the patches
manageable.
Signed-off-by: Adam Sampson <[email protected]>
Signed-off-by: Aleksei Mamlin <[email protected]>
Signed-off-by: Alexandru Gagniuc <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Emilio López <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Henrik Nordstrom <[email protected]>
Signed-off-by: Jens Kuske <[email protected]>
Signed-off-by: Luc Verhaegen <[email protected]>
Signed-off-by: Luke Leighton <[email protected]>
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Patrick Wood <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Wills Wang <[email protected]>
Signed-off-by: Ian Campbell <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Cc: Tom Cubie <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This patch adds DRAM initialisation support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.
Signed-off-by: Alexandru Gagniuc <[email protected]>
Signed-off-by: Emilio López <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Henrik Nordstrom <[email protected]>
Signed-off-by: Jens Kuske <[email protected]>
Signed-off-by: Luke Leighton <[email protected]>
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Siarhei Siamashka <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Ian Campbell <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Cc: Tom Cubie <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This patch adds the basic pinmux and gpio support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Ma Haijun <[email protected]>
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Henrik Nordström <[email protected]>
Signed-off-by: Ian Campbell <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Tom Cubie <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This patch adds the basic clocks and timer support for the Allwinner A20
(sun7i) processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.
Some of the code here is common to multiple sunxi subarchtectures, hence files
are named sun4i which is the earliest similar variant.
Signed-off-by: Alexandru Gagniuc <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Emilio López <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Henrik Nordstrom <[email protected]>
Signed-off-by: Jens Kuske <[email protected]>
Signed-off-by: Luke Leighton <[email protected]>
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Ian Campbell <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Tom Cubie <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.
Signed-off-by: Stefan Agner <[email protected]>
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