| Age | Commit message (Collapse) | Author |
|---|
|
During very early boot-ROM execution the pinmux
configuration isi in Hi-Z state. If pull-up is enabled
on GPIO pad's there will be a short period of toggle
from high to low on the IO when GPIO is set low during
boot. To avoid this glitch, disable pull-up configuration
in GPIO pinmux.
Signed-off-by: Bhuvanchandra DV <[email protected]>
|
|
I implemented a GPIO driver based on Driver Model for the UniPhier
SoC family, but I could not find any good reason why such SoC
specific GPIO headers are needed.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
|
|
This patch adds support for stm32f7 family & stm32f746 board.
Signed-off-by: Vikas Manocha <[email protected]>
|
|
Base addresses for GPIOs could be different for different socs, this
patch moves the base addresses from driver to the soc specific location.
Signed-off-by: Vikas Manocha <[email protected]>
|
|
This patch removes the gpio clock enable from gpio driver & move it in the
board code, making it possible to use the gpio driver with other socs.
Signed-off-by: Vikas Manocha <[email protected]>
|
|
The initialization for smmu and stream id is moved into the common soc
code.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
DDR erratum A-009942 applies to LS1043A.
Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
|
|
Add support for phy 1-3.
Signed-off-by: Jelle van der Waa <[email protected]>
[[email protected]: use setclrbits_le32 instead of read-modify-write]
Signed-off-by: Hans de Goede <[email protected]>
|
|
Remove unused macros. Adresses are taken from DT.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Reviewed-by: Moritz Fischer <[email protected]>
|
|
|
|
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.
arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.
Signed-off-by: Ye.Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.
arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.
Signed-off-by: Ye.Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Add the peripherals/masters definitions and registers base addresses
for mx7d RDC.
Signed-off-by: Ye.Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Add the definitions for the RDC mappings for i.MX6 SoloX.
Signed-off-by: Ye.Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Introduce Resource Domain Controller support for i.MX.
Now i.MX6SX and i.MX7D supports this feature to assign masters
and peripherals to different domains.
Signed-off-by: Ye.Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Introudce rdc regs structure and rdc sema reg structure for i.MX6.
For now, to i.MX6, only i.MX6SX supports this.
Signed-off-by: Ye.Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Refactored data structure for CAAM's job ring and Secure Memory
to support i.MX7.
The new memory map use macros to resolve SM's offset by version.
This will solve the versioning issue caused by the new version of
secure memory of i.MX7
Signed-off-by: Ulises Cardenas <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
|
|
Remove the old PWM code. Remove calls to CONFIG_LCD functions now that we
are using driver model for video.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
There is no need to have these in a separate file as they are not
referenced from anywhere else.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
Move this driver over to use driver model. This involves rearranging the
code somewhat. The effect is that everything is run from the probe() method.
Boards which use this are fixed up, but only seaboard is tested.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
We have a structure for the display panel and another for the controller.
There is some overlap between them. Merge them to simplify the driver.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
At present we have code in arch/arm and code in drivers/video. Move it all
into drivers/video since it is a display driver and our current approach is
to put all driver code in drivers/.
Make a few functions static now that they are not used outside the file.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
There isn't a lot of benefit of have two separate files. With driver model
the code needs to be in the same driver, so it's better to have it in the
same file.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
This PWM supports four channels. The driver always uses the 32KHz clock,
and adjusts the duty cycle accordingly.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
|
|
This enum is referenced from common/spl/spl.c.
Signed-off-by: Masahiro Yamada <[email protected]>
|
|
Add nand driver support for zynqmp. The Nand
controller used in ZynqMP is Arasan Nand Flash
controller.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
[scottwood: Fix checkpatch warning]
Signed-off-by: Scott Wood <[email protected]>
|
|
This patch removes the uart clock enable from serial driver & move it in the
board code.
Signed-off-by: Vikas Manocha <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
MAC address from fuse for ENET2.
Signed-off-by: Ye Li <[email protected]>
|
|
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
|
|
|
|
Valid for core A57
Signed-off-by: Ashish Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.
833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.
Signed-off-by: Ashish Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
Restore the old behavior of the MMU section entries configuration,
which is without the S-bit.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Simon Glass <[email protected]>
|
|
The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
set, it configures TTBR0 register. This register must be configured for the
cache on ARMv7 to operate correctly.
The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the
TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor
issues which are hard to replicate, for example certain USB sticks are not
detected or QSPI NOR sometimes fails to write pages completely.
The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is
correct because the code which added the test(s) for CONFIG_ARMV7 was added
shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was
not adjusted correctly to reflect that change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Simon Glass <[email protected]>
|
|
|
|
Enable the U-Boot Driver Model(DM) to use the Freescale QSPI driver.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal <[email protected]>
Acked-by: Ruchika Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
There are two phases in Secure Boot
1. ISBC: In BootROM, validate the BootLoader (U-Boot).
2. ESBC: In U-Boot, continuing the Chain of Trust by
validating and booting LINUX.
For ESBC phase, there is no difference in SoC's based on ARM or
PowerPC cores.
But the exit conditions after ISBC phase i.e. entry conditions for
U-Boot are different for ARM and PowerPC.
PowerPC:
If Secure Boot is executed, a separate U-Boot target is required
which must be compiled with a diffrent Text Base as compared to
Non-Secure Boot. There are some LAW and TLB settings which are
required specifically for Secure Boot scenario.
ARM:
ARM based SoC's have a fixed memory map and exit conditions from
BootROM are same irrespective of boot mode (Secure or Non-Secure).
Thus the current Secure Boot functionlity has been split into
two parts:
CONFIG_CHAIN_OF_TRUST
This will have the following functionality as part of U-Boot:
1. Enable commands like esbc_validate, esbc_halt
2. Change the environment settings based on bootmode, determined
at run time:
- If bootmode is non-secure, no change
- If bootmode is secure, set the following:
- bootdelay = 0 (Don't give boot prompt)
- bootcmd = Validate and execute the bootscript.
CONFIG_SECURE_BOOT
This is defined only for creating a different compile time target
for secure boot.
Traditionally, both these functionalities were defined under
CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement
for a separate Secure Boot target for ARM based SoC's.
CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be
determine at run time.
Another Security Requirement for running CHAIN_OF_TRUST is that
U-Boot environemnt must not be picked from flash/external memory.
This cannot be done based on bootmode at run time in current U-Boot
architecture. Once this dependency is resolved, no separate
SECURE_BOOT target will be required for ARM based SoC's.
Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is
defining CONFIG_ENV_IS_NOWHERE
Signed-off-by: Aneesh Bansal <[email protected]>
Acked-by: Ruchika Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was
earlier defined in all config files. The definition has been
moved to a common file which is included by all configs.
Signed-off-by: Aneesh Bansal <[email protected]>
Acked-by: Ruchika Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
The file fsl_secure_boot.h must be included in config file for
Secure Boot. This is not required to be protected by any macro.
CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be
turned on.
The above was missing in some config files and all files have been
made uniform in this respect.
Signed-off-by: Aneesh Bansal <[email protected]>
Acked-by: Ruchika Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
SD1 boot mode is using different bootmode values.
Add support for this mode used on DC1.
Signed-off-by: Michal Simek <[email protected]>
|
|
Modify the SD bootmode value to 0x3 as per latest
spec. Also add new boot mode QSPI 32 bit boot mode
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
|
|
Remove SECURE_IOU option which is not needed. U-Boot itself can detect
which EL level it is on and based on that use do platform setup.
It also simplify usage because one Kconfig entry is gone.
Signed-off-by: Michal Simek <[email protected]>
|
|
Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T.
Mostly the timing parameters are different from DDR3.
Signed-off-by: Vishnu Patekar <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
|
|
Different A83T boards have different DRAM types. Banapi M3 has LPDDR3,
Allwinner Homlet v1.2 has DDR3.
This adds groundwork to support for new DRAM type for A83T.
Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must
be set in respective board defconfig.
Signed-off-by: Vishnu Patekar <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
|
|
H3's CCU includes some switches which disable non-secure access to some
of the more critical clock controls, such as MBUS, PLLs, and main
platform busses.
Configure them to enable non-secure access.
For now the only SoC that has this feature is the H3. For other
platforms just use a default (weak) empty function so things do
not break.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
|
