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While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.
Fix this to mark the regions as XN by default.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Alexander Graf <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Add support for rk3288 dram capacity auto detect, support DDR3 and
LPDDR3, DDR2 is not supported.
The program will automatically detect:
- channel number
- rank number
- column address number
- row address number
The dts file do not need to describe those info after apply this patch.
Signed-off-by: Kever Yang <[email protected]>
Tested-by: Simon Glass <[email protected]>
Tested-by: Vagrant Cascadian <[email protected]>
Tested-by: Vagrant Cascadian <[email protected]>
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This function is called from outside the driver. It should be placed into
common SoC code. Move it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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This function is called from outside the driver. It should be placed into
common SoC code. Move it.
Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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This function is called from outside the driver. It should be placed into
common SoC code. Move it.
Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses
are at an offset of 0x200 within the SID address space.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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This is a cleaned up version set_pll() from Allwinner's boot0 source
(bootloader/basic_loader/bsp/bsp_for_a80/common/common.c).
[[email protected]: Added commit message; style cleanup]
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all applications (e.g. headless
systems might want to give priority to IO modules).
Adding a common callout to gtbus_init() from the SPL clock init
with a weakly defined implementation in sunxi/clock.c to fallback
to for platforms that don't require this.
[[email protected]: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.
With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.
[[email protected]: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai <[email protected]>
[[email protected]: Drop some huge non-documenting #if 0 ... #endif blocks]
[[email protected]: Fix checkpatch warnings]
Signed-off-by: Hans de Goede <[email protected]>
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Mostly by adding MACH_SUN50I to some existing #ifdefs enable support
for the the HCI0 USB host controller on the A64.
Fix up some minor 64-bit hiccups on the way.
Add the bare minimum DT bits to the A64 .dtsi and enable the controllers
and the PHY on the Pine64.
This is limited to the first USB controller at the moment, which is
connected to the lower USB socket on the Pine64 board.
[Andre: remove unneeded defines, enable OHCI, add commit message]
Signed-off-by: Amit Singh Tomar <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
common/Kconfig
configs/dms-ba16_defconfig
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Boot Log for i.CoreM6 DualLite/Solo Starter Kit:
-----------------------------------------------
U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1
U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)
CPU: Freescale i.MX6SOLO rev1.3 at 792MHz
CPU: Industrial temperature grade (-40C to 105C) at 31C
Reset cause: POR
DRAM: 256 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
switch to partitions #0, OK
mmc0 is current device
reading boot.scr
** Unable to read file boot.scr **
reading zImage
6741808 bytes read in 341 ms (18.9 MiB/s)
Booting from mmc ...
reading imx6dl-icore.dtb
30600 bytes read in 19 ms (1.5 MiB/s)
Booting using the fdt blob at 0x18000000
Using Device Tree in place at 18000000, end 1800a787
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
Boot Log for i.CoreM6 Quad/Dual Starter Kit:
--------------------------------------------
U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1
U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)
CPU: Freescale i.MX6Q rev1.2 at 792MHz
CPU: Industrial temperature grade (-40C to 105C) at 28C
Reset cause: POR
DRAM: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
icorem6qdl>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Acked-by: Peng Fan <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add mx7_plugin.S which calls boot rom setup function, generate the second ivt,
and jump back to boot rom.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Add mx6_plugin.S which calls boot rom setup function, generate the second ivt,
and jump back to boot rom.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Utkarsh Gupta <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Utkarsh Gupta <[email protected]>
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Using PSCI you can not only reset the system, you can also shut it down!
This patch exposes a function to do exactly that to whatever code wants
to make use of it.
Signed-off-by: Alexander Graf <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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All systems that are running on armv8 are running bare metal with firmware
that implements PSCI running in EL3. That means we don't really need to expose
the hypercall variants of them.
This patch leaves the code in, but makes the code explicit enough to have the
compiler optimize it out. With this we don't need to worry about hvc vs smc
calling convention when calling psci helper functions.
Signed-off-by: Alexander Graf <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
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Add silicon ID code for AM437x silicon. This can be used to print
the cpu info using CONFIG_DISPLAY_CPUINFO.
Also printing "CPU :" along with cpu name in order to be consistent
with other OMAP platforms.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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The normal longjmp command allows for a caller to pass the return value
of the setjmp() invocation. This patch adds that semantic to the arm
implementation of it and adjusts the efi_loader call respectively.
Signed-off-by: Alexander Graf <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The KeyStone platform has its own clk_get_rate() but its prototype
is different from that of the common-clk (clk-uclass) framework.
Prefix the KeyStone specific implementation with ks_ in order to
avoid name-space conflict.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Register definitions needed for configuring the
ePWM module.
Signed-off-by: Tomas Melin <[email protected]>
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On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.
Cc: [email protected]
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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These functions are needed in UBI/UBIFS on ZynqMP platform (ARM64).
Signed-off-by: Adam Oleksy <[email protected]>
Cc: Albert Aribaud <[email protected]>
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Fix various misspellings of:
* deprecated
* partition
* preceding,preceded
* preparation
* its versus it's
* export
* existing
* scenario
* redundant
* remaining
* value
* architecture
Signed-off-by: Robert P. J. Day <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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At present this is only used on ARM and sandbox, but it is just as
applicable to other architectures. Move the function prototype into the
generic SPL header.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Move DDR3, DDR4 and related config options to Kconfig and clean up
existing uses.
Signed-off-by: York Sun <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Move DDR3, DDR4 and realted options to Kconfig and clean up existing
uses.
Signed-off-by: York Sun <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Move these options to Kconfig and clean up existing uses.
Signed-off-by: York Sun <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Move this option to Kconfig and clean up existing uses.
NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.
Signed-off-by: York Sun <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.
Signed-off-by: York Sun <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This
option is used by Freescale Layerscape SoCs.
Signed-off-by: York Sun <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.
Signed-off-by: Hou Zhiqiang <[email protected]>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <[email protected]>
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The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu status" queries the
spin table with actual core position. Add functions to calculate
core position from core number, to correctly calculate offsets.
Tested on LS2080ARDB and LS1043ARDB.
Signed-off-by: York Sun <[email protected]>
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By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.
Signed-off-by: Tang Yuantian <[email protected]>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <[email protected]>
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The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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For i.MX6, the mux width is 4, not 3. So enlarge the width.
IOMUX_CONFIG_LPSR is changed from 0x8 to 0x20 to not use bit 3 of mux.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.
Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: "Benoît Thébaudeau" <[email protected]>
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Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage
is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop
MISC0 bit[6:4]) setting to 2b'110.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Bai Ping <[email protected]>
Cc: Stefano Babic <[email protected]>
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Update memory map address for mx6ull.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Cc: Stefano Babic <[email protected]>
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Update Clock settings and CCM register map for i.MX6ULL.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Cc: Stefano Babic <[email protected]>
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Introduce is_mx6ull macro.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add i.MX6ULL major cpu type.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Add iomux header file for i.MX6ULL.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Create a few public APIs which rely on secure world ROM/HAL
APIs for their implementation. These are intended to be used
to reserve a portion of the EMIF memory and configure hardware
firewalls around that region to prevent public code from
manipulating or interfering with that memory.
Signed-off-by: Daniel Allred <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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rockchip platform have a protocol to pass the the kernel reboot mode to bootloader
by some special registers when system reboot. In bootloader we should read it and take action.
We can only setup boot_mode in board_late_init becasue "setenv" need env setuped.
So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init"
to replace "board_late_init" in board file.
Signed-off-by: Jacob Chen <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Reference to kernel source code, rockchip pwm has three
type, we are using v2 for rk3288 and rk3399, so let's
update the register to sync with pwm_data_v2 in kernel.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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