| Age | Commit message (Collapse) | Author |
|---|
|
struct sunxi_prcm_reg is naturally packed. There is no need to define it as
packed. Defining it as packed leads to compilation errors with GCC 9.2.1:
CC arch/arm/lib/reloc_arm_efi.o
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
:qarch/arm/cpu/armv7/sunxi/psci.c:163:21: error: taking address of packed
member of ‘struct sunxi_prcm_reg’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
163 | sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
Remove __packed attribute from struct sunxi_prcm_reg.
Signed-off-by: Heinrich Schuchardt <[email protected]>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Fixes for 2020.01
-----------------
- imx8qxp_mek: increase buffer sizes and args number
- Fixes for imx7ulp
- imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
- colibri_imx7: reserve DDR memory for Cortex-M4
- vining2000: fixes and convert to ethernet DM
- imx8m: fix rom version check to unbreak some B0 chips
- tbs2910: Disable VxWorks image booting support
|
|
Make the PMU LDO configuration interface available to board code,
so that board code can reconfigure the internal LDOs of the SoC.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Eric Nelson <[email protected]>
|
|
i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for
the rpmsg communication. Both use cases need a fixed location of
memory reserved. For the rpmsg use case the reserved area needs
to be in sync with the kernel's hardcoded vring descriptor location.
Use the linux,usable-memory property to carve out 1MB of memory
in case the M4 core is running. Also make sure that the i.MX 7
specific rpmsg driver does not get loaded in case we do not carve
out memory.
Signed-off-by: Stefan Agner <[email protected]>
Signed-off-by: Igor Opaniuk <[email protected]>
Reviewed-by: Oleksandr Suvorov <[email protected]>
|
|
scg_a7_apll_init() is not called anywhere, so remove such dead code
Signed-off-by: Fabio Estevam <[email protected]>
|
|
This PWM driver can be used to support pwm functions
for on all Rockchip Socs.
The previous chips than RK3288 did not support polarity,
and register layout was different from the RK3288 PWM.
The RK3288 keep the current functions.
RK3328 and the chips after it, which can support hardware lock,
configure duty, period and polarity at next same period, to
prevent the intermediate temporary state.
Signed-off-by: David Wu <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
Some generic PX30 SoMs found in the wild use UART3 as their debug output
instead of UART2 (used for MMC) and UART5.
Make it possible to use UART3 as early debug output, with the associated
clock and pinmux configuration. Two sets of output pins are supported (M0/M1).
Future users should also note that the pinmux default in the dts is to use
the M1 pins while the Kconfig option takes M0 as a default.
Signed-off-by: Paul Kocialkowski <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
|
|
According to the PX30 TRM, the iomux registers come first, before the pull
and strength control registers.
Signed-off-by: Paul Kocialkowski <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
|
|
Although layerscape platforms reuse mxc_get_clock() of i.MX platforms,
eSDHC clock getting do not have to use it. It uses global data
gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more
than one eSDHC controllers on SoC, they use same reference clock.
Signed-off-by: Yangbo Lu <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
|
|
RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.
Signed-off-by: Andy Yan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.
Signed-off-by: Elaine Zhang <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
rockchip_reset_bind() already does the needed init for the reset
registers, only referenced the wrong cru structure.
So we can get rid of the open-coded reset init and just fix
the correct cru reference.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
Add core architecture code to support the px30 soc.
This includes a separate tpl board file due to very limited
sram size as well as a non-dm sdram driver, as this also has
to fit into the tiny sram.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.
Signed-off-by: Kever Yang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
Add headers needed by the upcoming px30 support, including two
new dt-binding headers taken from the Linux kernel.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
Update the calculation of the stride to support all the DRAM case.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
For there are some structures and functions are common for all rockchip SoCs,
migrate to use the common code so that we can clean up reduandent codes.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
RK3328 has a similar controller and phy with PX30, so we can use the
common driver for it and remove the duplicate codes.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.
For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
The noc register bit definition may be the same for different SoC while
the offset of the register may be different, add the struction
definition as common code.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
This sdram_phy_px30.c is based on PX30 SoC, the functions are common
for phy, other SoCs with similar hardware could re-use it.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common
for controller, other SoCs with similar hardware could re-use it.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
There are some function like os_reg setting, capacity detect functions,
can be used as common code for different Rockchip SoCs, add a
sdram_common.c for all these functions.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
Since we have new DRAM type and to support different DRAM size in different
CS, we need more bits, so introduce sys_reg3 to record the info.
Note that the info in sys_reg3 is extension to sys_reg2 and the info in
sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as
VERSION2.
All the ENC macro are moved to sdram_common.h since the sdram.c only
need to do the info decode.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
The sdram.h suppose to be helper file for sdram.c which including dram
size decode and some u-boot related dram init interface, and all
structure and function for dram driver move to sdram_common.h
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c;
so that we can use the file name sdram_common.c in dram driver for
better understand the code;
clean the related file who has use the header file at the same time.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
The header file sdram.h is used for rk3288 and similar SoCs, rename it
to make it more understandable.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191105
-------------------
i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.
|
|
- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
fsl-layerscape, pci, icid, PSCI
|
|
Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.
Signed-off-by: Simon South <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
|
|
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Horia Geanta <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
|
|
LX2160A chips have 4 sata controllers. Add missing base addresses for
SATA3 and SATA4.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Horia Geanta <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
|
|
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below
compilation error appears
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function)
Fix it by wrapping with CONFIG_IS_ENABLED().
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Horia Geanta <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
|
|
Provide optimized memcpy_{from,to}io() and memset_io(). This is required
when moving large amount of data to and from IO regions such as IP
registers or accessing memory mapped flashes.
Code is borrowed from Linux Kernel v5.4.
Signed-off-by: Vignesh Raghavendra <[email protected]>
Reviewed-by: Lokesh Vutla <[email protected]>
|
|
i.MX8MN support loading images with rom api, so we implement
reuse board_return_to_bootrom to let ROM loading images.
Signed-off-by: Peng Fan <[email protected]>
|
|
Add pin header for i.MX8MN
Signed-off-by: Peng Fan <[email protected]>
|
|
i.MX8MN does not have LVTTL, it has a PE property
Signed-off-by: Peng Fan <[email protected]>
|
|
i.MX8MN has similar architecture with i.MX8MM, so it could reuse
the clock code of i.MX8MM, but i.MX8MN has different CCM root
configurations, so need a separate root entry.
Signed-off-by: Peng Fan <[email protected]>
|
|
Add a dummy cpu type and support get_cpu_rev for i.MX8MN
Signed-off-by: Peng Fan <[email protected]>
|
|
Add support for updating FCB/DBBT on i.MX7:
- additional new fields in FCB structure
- Leverage hardware BCH/randomizer for writing FCB
Signed-off-by: Igor Opaniuk <[email protected]>
Tested-by: Max Krummenacher <[email protected]>
Reviewed-by: Oleksandr Suvorov <[email protected]>
|
|
Extend GPMI Integrated ECC Control Register Description, include
additional defines for enabling randomizer function and providing
proper randomizer type.
For additional details check i.MX7 APR, section
9.6.6.3 GPMI Integrated ECC Control Register Description
(GPMI_ECCCTRLn)
Signed-off-by: Igor Opaniuk <[email protected]>
Tested-by: Max Krummenacher <[email protected]>
Reviewed-by: Oleksandr Suvorov <[email protected]>
|
|
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ,
so update the interface to add new argument.
Signed-off-by: Ye Li <[email protected]>
[agust: fixed imx8m-power-domain build]
Signed-off-by: Anatolij Gustschin <[email protected]>
Reviewed-by: Patrick Wildt <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
|
|
Add init_nand_clk to enable gpmi nand clock. Since i.MX8MQ not use CCF,
so we still use legacy mode to configure the clock.
Signed-off-by: Peng Fan <[email protected]>
|
|
imx6_is_bmode_from_gpr9 always returns false, because
IMX6_SRC_GPR10_BMODE is 1<<28 and gets casted to u8 on return.
This moves the function body into imx6_src_get_boot_mode, since that is the
only one using it and it is on the same abstraction level (accessing
registers directly).
Signed-off-by: Claudius Heine <[email protected]>
|
|
Introduce disable_ipu_clock(). This is done in preparation for
configuring the NoC registers on i.MX6QP in SPL.
Afer the NoC registers are set the IPU clocks can be disabled.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
|
|
The Allwinner H6 SoC has a register to set the PIO banks' voltage. When
it mismatches the real voltage supplied to the VCC to the PIO supply,
the PIO will work improperly.
The PIO controller also has a register that contains the status of each
VCC rail of the PIO supplies, and it has the same definition with the
configuration register. so we can just copy the content of this register
to the configuration register at startup, to ensure the configuration is
correct at startup stage.
Signed-off-by: Icenowy Zheng <[email protected]>
[jagan: s/__maybe__unused/__maybe_unused]
Signed-off-by: Jagan Teki <[email protected]>
Acked-by: Jagan Teki <[email protected]>
|
|
Half DQ configuration seems to be very rare for H6 based boards/STBs,
but exists nevertheless. Currently the only known product which needs
this support is Tanix TX6 mini.
This commit adds support for half DQ configuration. Code was tested
for regressions on other configurations (OrangePi 3 1 GiB/LPDDR3, Tanix
TX6 4 GiB/DDR3) and none were found.
Thanks to Icenowy Zheng for help with this code.
Reviewed-by: Andre Przywara <[email protected]>
Tested-by: thomas graichen <[email protected]>
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Maxime Ripard <[email protected]>
|
|
LX2160A/LX2120A/LX2080A SVR value should be
0x873600/0x873620/0x873602
Previous values were valid only if CAN fuse is blown.
Signed-off-by: Wasim Khan <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
|
