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One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.
Signed-off-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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K2G supports various sysclk frequencies which can be
determined using sysboot pins. PLLs should be configured
based on this sysclock frequency. Add PLL configurations
for all supported sysclk frequencies.
Signed-off-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The KeyStone platform has its own clk_get_rate() but its prototype
is different from that of the common-clk (clk-uclass) framework.
Prefix the KeyStone specific implementation with ks_ in order to
avoid name-space conflict.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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These two functions are neither defined nor referenced.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
Timer5(dedicated to ARM) when used as WatchDog timer, the events it
generates are routed to the above mux.
Following are the 3 events that can controlled bt the reset mux:
- Device Reset
- An interrupt to the ARM_GIC
- An interrupt to the ARM_GIC followed by a device reset.
Right now to give a default watchdog behaviour "Device reset" is
being selected.
Signed-off-by: Lokesh Vutla <[email protected]>
Acked-by: Nishanth Menon <[email protected]>
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Add missing Privilege ID settings for KS2 SoCs.
Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)
Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K | K2L | K2E | K2G
-------+-----------+-----------+-----------+---------
0 | C66x 0 | C66x 0 | C66x 0 | C66x 0
1 | C66x 1 | C66x 1 | Reserved | ARM
2 | C66x 2 | C66x 2 | Reserved | ICSS0
3 | C66x 3 | C66x 3 | Reserved | ICSS1
4 | C66x 4 | Reserved | Reserved | NETCP
5 | C66x 5 | Reserved | Reserved | CPIE
6 | C66x 6 | Reserved | Reserved | USB
7 | C66x 7 | Reserved | Reserved | Reserved
8 | ARM | ARM | ARM | MLB
9 | NetCP | NetCP | NetCP | PMMC
10 | QM_PDSP | QM_PDSP | QM_PDSP | DSS
11 | PCIe_0 | PCIe_0 | PCIe_0 | MMC
12 | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP
13 | Reserved | Reserved | PCIe_1 | Reserved
14 | HyperLink | PCIe_1 | HyperLink | Reserved
15 | Reserved | Reserved | TSIP | Reserved
-------+-----------+-----------+-----------+---------
NOTE: Few of these might have default configurations, however,
since most are software configurable, it is better to explicitly
configure the system to have a known default state.
Without programming these, we end up seeing lack of coherency on certain
peripherals resulting in inexplicable failures (such as USB peripheral's
DMA data not appearing on ARM etc and weird workarounds being done by
drivers including cache flushes which tend to have system wide
performance impact).
By marking these segments as shared, we also ensure SoC wide coherency
is enabled.
Reported-by: Bin Liu <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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MSMC segment Privilege ID is not consistent accross the keystone2 SoCs.
As the first step to ensure complete SoC wide coherency setup, lets
refactor the macros to remove the #if-deffery around the code which
obfuscates which IDs are actually enabled for which SoC.
As a result of this change the PCIe configuration is moved after the
msmc configuration is complete, but that should ideally have no
functional impact.
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Fix up BOOT_SET_BITFIELD to be a static inline function to be readable
with the same functionality.
Reported-by: Tom Rini <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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BOOT_READ_BITFIELD can easily be a static inline function and be a
little more readable with the same functionality.
Reported-by: Tom Rini <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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BOOTBITMASK is almost impossible to decode, so convert it into a simpler
static line functions of equivalent solution.
Reported-by: Tom Rini <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case, we split the code for
supporting the monitor out from the code for loading it.
Cc: Vitaly Andrianov <[email protected]>
Cc: Nishanth Menon <[email protected]>
Cc: Lokesh Vutla <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Because KS2 u-boot works in 32 bit address space the existing ram_size
global data field cannot be used. The maximum, which the get_ram_size()
can detect is 2GB only. The ft_board_setup() needs the actual ddr3 size
to fix up dtb.
This commit introduces the ddr3_get_size() which uses SPD data to
calculate the ddr3 size. This function replaces the "ddr3_size"
environment variable, which was used to get the SODIMM size.
For platforms, which don't have SODIMM with SPD and ddr3 is populated to
a board a simple ddr3_get_size function that returns ddr3 size has to be
implemented. See hardware-k2l.h
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This commit replaces hard-coded EMIF and PHY DDR3 configurations for
predefined SODIMMs to a calculated configuration. The SODIMM parameters
are read from SODIMM's SPD and used to calculated the configuration.
The current commit supports calculation for DDR3 with 1600MHz and 1333MHz
only.
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The maximum device and arm speeds can be determined by reading
EFUSE_BOOTROM register. As there is already a framework for reading this
register, adding support for all possible speeds on k2g devices.
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Its not compulsory that speed definition should be same on EFUSE_BOOTROM
register for all keystone 2 devices. So, allow for board specific
speed definitions.
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The DSPs are powered on by default upon a Power ON reset, and
they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E
during the boot in u-boot. This is not functional on K2G though.
Extend the existing DSP power-off support to the only DSP present
on K2G. Do note that the PSC clock domain module id for DSP on K2G
differs from that of previous Keystone2 SoCs.
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Define a macro for the DSP GEM power domain id number and
use it instead of a hard-coded number in the code that
disables all the DSPs on various Keystone2 SoCs.
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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These are useful for modules that need to be held in reset and are
enabled for data to be loaded on to them. Typically these are
microcontrollers or other processing entities in the system.
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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'#define X a | b' is better defined as '#define X (a | b)' for obvious
reasons.
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Add MMC support for k2g
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Tested-by: Mugunthan V N <[email protected]>
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update K2G nav rx queue number
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Mugunthan V N <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Coreect base addresses for SPI, Queue Manager, Ethernet, GPIO,
and MSMC segments.
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Add api for configuring pin mux.
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Add ddr3 related info
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Add psc information for k2g
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Add clock information for Galileo
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Mugunthan V N <[email protected]>
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Add pll data for k2g
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Adding CPU detection support for Keystone2 Galileo.
Signed-off-by: Lokesh Vutla <[email protected]>
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On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <[email protected]>"
and based on the previous work done by "Hao Zhang <[email protected]>"
Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <[email protected]>
Tested-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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introduce BIT() definition, used in at91_udc gadget
driver.
Signed-off-by: Heiko Schocher <[email protected]>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <[email protected]>
Acked-by: Stefan Roese <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
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ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.
Thanks to "Vitaly Andrianov <[email protected]>" for bisecting this issue
Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection")
Tested-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Remove unused external clocks and make a common definition
for all keystone platforms.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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This is just a cosmetic change that makes
the calling of pll init code looks much cleaner.
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Use common devspeed and armspeed definitions.
Also fix reading efuse bootrom register.
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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There are two types of PLL for all keystone platforms:
Main PLL, Secondary PLL. Instead of duplicating the same definition
for each secondary PLL, have a common function which does
initialization for both PLLs. And also add proper register
definitions.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Add proper register definition for JTAG ID and
cleanup cpu_is_* functions.
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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Move arch/arm/include/asm/arch-keystone/*
-> arch/arm/mach-keystone/include/mach/*
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Tom Rini <[email protected]>
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