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Instead of having a peripheral clock of 50 MHz like the BCM63xx family, it
has a 48 MHz clock.
This fixes uart baud rate calculation for BCM3380.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver allows rebooting the SoC by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver allows rebooting the SoC by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver allows rebooting the SoC by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver controls the watchdog present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver controls the watchdog present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver controls the watchdog present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The boston memory map isn't suited to the simple "all memory starting
from 0" approach that the MIPS arch_fixup_fdt() implementation takes.
Instead we need to indicate the first 256MiB of DDR from 0 and the rest
from 0x90000000. Implement ft_board_setup to do that.
Signed-off-by: Paul Burton <[email protected]>
Signed-off-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Move the MIPS Coherence Manager (CM) Global Configuration Registers
(GCRs) away from the region of the physical address space which the
Boston board's parallel flash is found in, such that we can access all
of flash without clobbering GCRs.
Signed-off-by: Paul Burton <[email protected]>
Signed-off-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Without adding a prompt for CONFIG_MIPS_CM_BASE, Kconfig doesn't allow
defconfigs to set it. Provide the prompt in order to allow for that.
Signed-off-by: Paul Burton <[email protected]>
Signed-off-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Fixes commit a186d26, which missed including SFR NeufBox config from bmips
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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Shrink brcm,bcm6328-mc size to avoid overlapping with other controllers
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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Shrink brcm,bcm6328-mc size to avoid overlapping with other controllers
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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Shrink brcm,bcm6358-mc size to avoid overlapping with other controllers
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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This driver can control up to 32 power domains.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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This driver can control up to 32 power domains.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 resets.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This serves as an example for bcm6358-leds.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 32 serial leds.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This board has several LEDs attached to its BCM6328 led controller.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This board has several LEDs attached to its BCM6328 led controller.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 24 LEDs and supports HW blinking and serial leds.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver can control up to 24 LEDs and supports HW blinking and serial leds.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This board has several LEDs attached to gpio0.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This SoC has one gpio bank divided into two 32 bit registers, with a total of
52 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This SoC has one gpio bank with a total of 32 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This SoC has one gpio bank divided into two 32 bit registers, with a total of
40 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Avoid duplicating do_reset definition if SYSRESET is enabled for MIPS
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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All MIPS boards that support debug uart are calling debug_uart_init right at
the beginning of board_early_init_f.
Instead of doing that, let's provide a generic call to debug_uart_init right
before the call to board_init_f if debug uart is enabled for boards without
stack in SRAM.
On the other hand, boards with stack in SRAM can call earlier (right before
low level init).
Signed-off-by: Daniel Schwierzeck <[email protected]>
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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Define PLATFORM_ELFFLAGS for MIPS in order to be able to generate u-boot.elf
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.
Signed-off-by: Simon Glass <[email protected]>
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini <[email protected]>
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