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2011-05-12PPC405EX CHIP_21 erratumSteven A. Falco
APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated 4/27/11) states that rev D processors may wake up with the wrong feature set. This patch implements the APM-proposed workaround. To enable this patch for your board, add the appropriate define for your CPU to your board header file. See kilauea.h for more information. The following variants are supported: #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY Please note that if you select the wrong define, your board will not boot, and JTAG will be required to recover. Tested on custom boards using: CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <[email protected]> CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <[email protected]> Signed-off-by: Steve Falco <[email protected]> Acked-by: Dirk Eibach <[email protected]> Signed-off-by: Stefan Roese <[email protected]>
2011-04-29powerpc: eSPI and eSPI controller supportMingkai Hu
Signed-off-by: Mingkai Hu <[email protected]> Singed-off-by: Jerry Huang <[email protected]> Signed-off-by: Shaohui Xie <[email protected]> Cc: Mike Frysinger <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-28powerpc/85xx: Change timebase divisor to be defined per processorKumar Gala
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala <[email protected]>
2011-04-28powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001Timur Tabi
Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1 are swapped. Erratum SERDES-A001 says that if bank two is kept disabled and after bank three is enabled, then the PLL for bank three won't lock properly. The work-around is to enable and then disable bank two after bank three is enabled. Signed-off-by: Timur Tabi <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-28powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORATimur Tabi
Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-28powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005Timur Tabi
SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-27powerpc/85xx: Don't set FT_FSL_PCI_SETUP if CONFIG_PCI is not setMatthew McClintock
A lot of boards set FT_FSL_PCI_SETUP directly in their board code and don't check to see if CONFIG_PCI is actually defined. This will cause the board compilation to fail if CONFIG_PCI is not defined. The p1022ds board is one such example. Instead of fixing every board this patch wraps FT_FSL_PCI_SETUP around CONFIG_PCI so we can remove CONFIG_PCI and boards will still build properly. Signed-off-by: Matthew McClintock <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-27powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" propertiesKim Phillips
versioned SEC properties changed names during development, so for now search and update LIODNs for both "secX.Y" and "sec-vX.Y" based properties. Signed-off-by: Kim Phillips <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-27powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCsLei Xu
The workaround for ESDHC111 should also be applied on P2040/P3041/P5010/P5020 SoCs. Signed-off-by: Lei Xu <[email protected]> Signed-off-by: Roy Zang <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-27powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020Roy Zang
The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-27powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)Kumar Gala
The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <[email protected]> Signed-off-by: Shaohui Xie <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-27p4080/serdes: Implement the XAUI workaround for SERDES9 erratumEmil Medve
Signed-off-by: Emil Medve <[email protected]> Signed-off-by: Timur Tabi <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-27powerpc/85xx: fsl_corenet_serdes code reworkEmil Medve
Rework and add some new APIs to the fsl_corenet_serdes code for use by erratum and drivers. * Rename serdes_get_bank() to serdes_get_bank_by_lane() * Add serdes_get_first_lane returns which SERDES lane is used by device Signed-off-by: Emil Medve <[email protected]> Signed-off-by: Timur Tabi <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-27powerpc/85xx: Add device tree fixup for bman portalHaiying Wang
Fix fdt bportal to pass the bman revision number to kernel via device tree. Signed-off-by: Haiying Wang <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-27powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdbRamneek Mehresh
Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <[email protected]>
2011-04-27powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoCDipen Dudhat
Signed-off-by: Dipen Dudhat <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-28powerpc: fix implementation of out_8 to match the other out_XX functionsTimur Tabi
Signed-off-by: Timur Tabi <[email protected]>
2011-04-20fsl: Change fsl_phy_enet_if to phy_interface_tAndy Fleming
The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum. This meant that drivers which used fsl_phy_enet_if to deal with PHY interfaces would have to convert between the two (or we would have to have them mirror each other, and deal with the ensuing maintenance headache). Instead, we switch all clients of fsl_phy_enet_if over to phy_interface_t, which should become the standard, anyway. Signed-off-by: Andy Fleming <[email protected]> Acked-by: Detlev Zundel <[email protected]>
2011-04-20tsec: Convert tsec to use PHY LibAndy Fleming
This converts tsec to use the new PHY Lib. All of the old PHY support is ripped out. The old MDIO driver is split off, and placed in fsl_mdio.c. The initialization is modified to initialize the MDIO driver as well. The powerpc config file is modified to configure PHYLIB if TSEC_ENET is configured. Signed-off-by: Mingkai Hu <[email protected]> Signed-off-by: Andy Fleming <[email protected]> Signed-off-by: Kumar Gala <[email protected]> Acked-by: Detlev Zundel <[email protected]>
2011-04-10fsl_esdhc: Deal with watermark level register related changesPriyanka Jain
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <[email protected]> Signed-off-by: Poonam Aggrwal <[email protected]> Tested-by: Stefano Babic <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-10powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DSJiang Yutang
For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-05powerpc/85xx: Add some defines & registers in immap_85xx.hZhao Chenhui
* Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-05powerpc/85xx: Add P1021 specific QE and UEC supportHaiying Wang
P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-05powerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOTZhao Chenhui
Signed-off-by: Zhao Chenhui <[email protected]> Acked-by: Li Yang <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020Laurentiu TUDOR
We utilize the compatible string to find the node to add fsl,liodn property to. However P3041 & P5020 don't have "fsl,p4080-pcie" compatible for their PCIe controllers as they aren't backwards compatible. Allow the macro's to specify the PCIe compatible to use to allow SoC uniqueness. On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the PCIe controllers. Signed-off-by: Laurentiu TUDOR <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Fixup determining PME, FMan freqKumar Gala
On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some additional rules to determining the various frequencies that PME & FMan IP blocks run at. We need to take into account: * Reduced number of Core Complex PLL clusters * HWA_ASYNC_DIV (allows for /2 or /4 options) On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs the PME & FMan blocks utilize the second Core Complex PLL. On SoCs like p4080 with 4 Core Complex PLLs we utilize the third Core Complex PLL for PME & FMan blocks. On P2040/P3041/P5020 we have the added feature that we can divide the PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080 this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be set to 0 and this gets a backward compatiable /2 behavior. Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZEKumar Gala
CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in config_mpc85xx.h for those parts with a Frame Manager. Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Adds some P1010/P1014 SoC configuration definesPoonam Aggrwal
Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR and SDHC erratum. Signed-off-by: Poonam Aggrwal <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Support for Freescale P1024/P1025 processorKumar Gala
Add Support for Freescale P1024/P1025 (dual core) and P1015/P1016 (single core) processors. P1024 is a variant of P1020 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA P1025 is a variant of P1021 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA P1015 is a variant of P1024 processor with single core and P1016 is a variant of P1025 processor with single core. Added comments in config_mpc85xx.h to denote single core versions of processors. Signed-off-by: Jin Qing <[email protected]> Signed-off-by: Li Yang <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-04fsl_ddr: Adds 16 bit DDR Data width optionPoonam Aggrwal
Signed-off-by: Poonam Aggrwal <[email protected]> Cc: York Sun <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-04fsl_pci: Add support for FSL PCIe controllers v2.xPrabhakar Kushwaha
FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Refactor Qman/Portal support to be shared between SoCsHaiying Wang
There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Add support for Freescale P1023/P1017 ProcessorsRoy Zang
Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Cleanup some QE related definesKumar Gala
Move some processor specific QE defines into config_mpc85xx.h and use QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct. Also fixed up some comment style issues in immap_qe.h Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020Kumar Gala
Specify the number of DDR controllers, number of frame managers, number of 1g and 10g ports. Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>Kumar Gala
Remove declerations of fsl_ddr_set_memctl_regs in board files with and place it into a common header. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Add support for Integrated Flash Controller (IFC)Dipen Dudhat
The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <[email protected]> Acked-by: Scott Wood <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-04-04powerpc/85xx: Add SERDES support for P1010/P1014Prabhakar Kushwaha
Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-03-29powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCsPrabhakar Kushwaha
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-03-28powerpc/85xx: Enable various errata on P1022/P1013 SoCsJiang Yutang
Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs. Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2. Signed-off-by: Jiang Yutang <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-03-24powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address ParityYork Sun
To recognize DIMMs with ECC capability by testing ECC bit only. Not to be confused by Address Parity bit. Signed-off-by: York Sun <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-02-09Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk
2011-02-07ppc4xx: Add DLVision-10G board supportDirk Eibach
Board support for the Guntermann & Drunck DLVision-10G. Adds support for multiple FPGAs per board for gdsys 405ep architecture. Adds support for dual link osd hardware for gdsys 405ep. Signed-off-by: Dirk Eibach <[email protected]> Signed-off-by: Stefan Roese <[email protected]>
2011-02-03powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134York Sun
Workaround for the following errata: DDR111 - MCKE signal may not function correctly at assertion of HRESET DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can calibrate to incorrect values These two workarounds must be implemented together because they touch common registers. Signed-off-by: York Sun <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-02-03powerpc/85xx: Rename MPC8572 DDR erratum to DDR115York Sun
Use unique erratum number instead of platform number. Enable command that reports errata on MPC8572DS. Signed-off-by: York Sun <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-02-03fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)Kumar Gala
Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8, and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13. Signed-off-by: Kumar Gala <[email protected]>
2011-02-03powerpc/85xx: Enable ESDHC111 Erratum on P2010/P2020 SoCsKumar Gala
Signed-off-by: Kumar Gala <[email protected]>
2011-02-02Minor Coding Style Cleanup.Wolfgang Denk
Signed-off-by: Wolfgang Denk <[email protected]>
2011-01-19corenet_ds: Extend board specific parametersYork Sun
Extend board specific parameters to include cpo, write leveling override Extend write leveling sample to 0xf Adding rcw overrid for quad-rank RDIMMs Signed-off-by: York Sun <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2011-01-19mpc85xx: Implement workaround for erratum DDR-A003York Sun
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
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