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With some versions of gcc (that we know of 4.6.3 and 4.8.2 are affected)
it is necessary to specify --bss-plt to get the final blrl in the
_GOT2_TABLE_. Without this the last symbol does not get it's address
relocated. For the P2041RDB board this ended up being
NetArpWaitTimerStart which caused the ARP packets to timeout
immediately.
Signed-off-by: Joakim Tjernlund <[email protected]>
Signed-off-by: Chris Packham <[email protected]>
Acked-by: Joakim Tjernlund <[email protected]>
Acked-by: Scott Wood <[email protected]>
Reviewed-by: York Sun <[email protected]>
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U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.
Signed-off-by: York Sun <[email protected]>
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Each CPU of PowerPC has its default linker script under the CPU
directory, except mpc8xx.
Every mpc8xx board has its own linker script under the board
directory, resulting in lots of duplication of linker scripts.
I notice eight mpc8xx boards have the same linker script.
We can decrease the number of linker scripts by putting a single
default linker script, arch/powerpc/cpu/mpc8xx/u-boot.lds.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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"0x00" is a valid serdes protocol for QorIQ parts, and can not be
used to test whether the serdes is enabled or disabled.
Signed-off-by: Ebony Zhu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Fix following issues in USB device-tree fixup:
- returns when either dr_mode or phy_type not defined.
This was terminating fix-up when only either property
was defined in hwconfig string
- updates dr_mode_type or dr_phy_type with junk value when
their index is -1. Now these are updated only when their
respective index is pointing to relevant types
in modes[] and phys[] array
- dr_mode_type and dr_phy_type were not NULL for
each controller
Signed-off-by: Ramneek Mehresh <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.
We can delete the ones in arch and board Kconfig files.
This commit can be easily reproduced by the following command:
find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
N
s/\n[[:space:]]*string//
}
'
Signed-off-by: Masahiro Yamada <[email protected]>
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fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil <[email protected]>
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Some drivers (e.g. net/e1000) reference these functions. So, this
fixes the build of MVBC_P board.
I'm not familiar with the MPC5xxx platform, maybe a full
implementation shall be implemented instead of this stub in the
future.
Signed-off-by: Vasili Galka <[email protected]>
Cc: Wolfgang Denk <[email protected]>, Marek Vasut <[email protected]>
Acked-by: Wolfgang Denk <[email protected]>
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This board has been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada <[email protected]>
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These boards have been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada <[email protected]>
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This board has been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada <[email protected]>
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This board has been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada <[email protected]>
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This board has been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada <[email protected]>
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If hwconfig does not contains "en_cpc" then by default all cpcs are enabled
If this config is defined then only those individual cpcs which are defined
in the subargument of "en_cpc" will be enabled e.g en_cpc:cpc1,cpc2; (this
will enable cpc1 and cpc2) or en_cpc:cpc2; (this enables just cpc2)
Signed-off-by: Shaveta Leekha <[email protected]>
Signed-off-by: Sandeep Singh <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add deep sleep support in SPI/SD boot. The destination address
second stage uboot image is loaded to is changed because
currently this address will be used by kernel which means
we can't reserve it for resume.
Entry point to kernel is still placed in second stage uboot.
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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bootflag as a parameter is passed to board_init_f().
But it is not actually used in this function.
Make it effective by assigned it to gd->flags.
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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When CONFIG_WATCHDOG is defined the board initialization just performs
a WATCHDOG_RESET, an initialization of the watchdog is not done.
This has been modified fot the MPC85xx, the board initialization calls
its watchdog initialitzation allowing for full watchdog configuration
very early in the boot phase.
Signed-off-by: Rainer Boschung <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Function to inititialize the cpu watchdog added.
Signed-off-by: Rainer Boschung <[email protected]>
[York Sun: Add prototype in watchdog.h]
Reviewed-by: York Sun <[email protected]>
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For e500mc cores the watchdog timer period has to be set by means of a
6bit value, that defines the bit of the timebase counter used to signal
a watchdog timer exception on its 0 to 1 transition.
The macro used to set the watchdog period TCR_WP, was redefined for e500mc
to support 6 WP setting.
The parameter (x) given to the macro specifies the prescaling factor of
the time base clock (fTB):
watchdog_period = 1/fTB * 2^x
Signed-off-by: Rainer Boschung <[email protected]>
Reviewed-by: York Sun <[email protected]>
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TCR watchdog bit are overwritten when dec interrupt is enabled.
This has been fixed with this patch.
Signed-off-by: Rainer Boschung <[email protected]>
Reviewed-by: York Sun <[email protected]>
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CONFIG_${CPU} is defined by Kconfig.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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CONFIG_${ARCH} is defined by Kconfig.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This commit enables Kconfig.
Going forward, we use Kconfig for the board configuration.
mkconfig will never be used. Nor will include/config.mk be generated.
Kconfig must be adjusted for U-Boot because our situation is
a little more complicated than Linux Kernel.
We have to generate multiple boot images (Normal, SPL, TPL)
from one source tree.
Each image needs its own configuration input.
Usage:
Run "make <board>_defconfig" to do the board configuration.
It will create the .config file and additionally spl/.config, tpl/.config
if SPL, TPL is enabled, respectively.
You can use "make config", "make menuconfig" etc. to create
a new .config or modify the existing one.
Use "make spl/config", "make spl/menuconfig" etc. for spl/.config
and do likewise for tpl/.config file.
The generic syntax of configuration targets for SPL, TPL is:
<target_image>/<config_command>
Here, <target_image> is either 'spl' or 'tpl'
<config_command> is 'config', 'menuconfig', 'xconfig', etc.
When the configuration is done, run "make".
(Or "make <board>_defconfig all" will do the configuration and build
in one time.)
For futher information of how Kconfig works in U-Boot,
please read the comment block of scripts/multiconfig.py.
By the way, there is another item worth remarking here:
coexistence of Kconfig and board herder files.
Prior to Kconfig, we used C headers to define a set of configs.
We expect a very long term to migrate from C headers to Kconfig.
Two different infractructure must coexist in the interim.
In our former configuration scheme, include/autoconf.mk was generated
for use in makefiles.
It is still generated under include/, spl/include/, tpl/include/ directory
for the Normal, SPL, TPL image, respectively.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This commit adds:
- arch/${ARCH}/Kconfig
provide a menu to select target boards
- board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig
set CONFIG macros to the appropriate values for each board
- configs/${TARGET_BOARD}_defconfig
default setting of each board
(This commit was automatically generated by a conversion script
based on boards.cfg)
In Linux Kernel, defconfig files are located under
arch/${ARCH}/configs/ directory.
It works in Linux Kernel since ARCH is always given from the
command line for cross compile.
But in U-Boot, ARCH is not given from the command line.
Which means we cannot know ARCH until the board configuration is done.
That is why all the "*_defconfig" files should be gathered into a
single directory ./configs/.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
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The generic board infrastructure assumes that gd is set by
arch code.
Signed-off-by: Dirk Eibach <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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At present stdio device functions do not get any clue as to which stdio
device is being acted on. Some implementations go to great lengths to work
around this, such as defining a whole separate set of functions for each
possible device.
For driver model we need to associate a stdio_dev with a device. It doesn't
seem possible to continue with this work-around approach.
Instead, add a stdio_dev pointer to each of the stdio member functions.
Note: The serial drivers have the same problem, but it is not strictly
necessary to fix that to get driver model running. Also, if we convert
serial over to driver model the problem will go away.
Code size increases by 244 bytes for Thumb2 and 428 for PowerPC.
22: stdio: Pass device pointer to stdio methods
arm: (for 2/2 boards) all +244.0 bss -4.0 text +248.0
powerpc: (for 1/1 boards) all +428.0 text +428.0
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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When resume from deep sleep, uboot needs to enable L2 and CPC
cache, or they would be keeping unusable in kernel because
kernel didn't enble or initialized them.
This patch didn't change the existing L2 cache enabling code,
just put them in a function.
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Shaveta Leekha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.
Signed-off-by: Shaohui Xie <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.
Signed-off-by: York Sun <[email protected]>
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G4060 has no PA cores, hence removing its support.
Signed-off-by: Sandeep Singh <[email protected]>
Reviewed-by: York Sun <[email protected]>
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ls1021 is arm-core and supports qe too.
Move immap_qe.h into common directory for both arm and powerpc.
Signed-off-by: Zhao Qiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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On some SoC(e.g. T2080/T4240) the 3rd DMA is not functional if SRIO2 is
chosen. we add fdt_fixup_dma3() to disable the 3rd DMA if SRIO2 is chosen.
Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Since ARRAY_SIZE macro is defined in include/common.h,
re-defining it in arch-specific files is redundant.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Stefan Roese <[email protected]>
Acked-by: Sonic Zhang <[email protected]>
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This board is old enough and has no maintainer.
Signed-off-by: Masahiro Yamada <[email protected]>
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These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada <[email protected]>
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These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada <[email protected]>
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These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada <[email protected]>
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These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada <[email protected]>
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Remove the common infrastructure of nand_spl and
clean-up the code inside ifdef(CONFIG_NAND_U_BOOT)..endif.
Signed-off-by: Masahiro Yamada <[email protected]>
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This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to store address of CCSR space
which lies beyond 32 bit address range. This workaround
creats a LAW to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if "tdm" is defined in hwconfig.
Also disable POST tests and add LIODN for TDM
Signed-off-by: Sandeep Singh <[email protected]>
Reviewed-by: York Sun <[email protected]>
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SerDes PLL is calibrated at reset. When the junction temperature
delta from the time the PLL is calibrated exceeds +56C/-66C,
jitter may increase and can cause PLL to unlock.
This workaround overwrite the SerDes registers with new values,
to calibrate SerDes registers.
These values are known to work fine for all temperature ranges.
This workaround is valid for B4, T4 and T2 platforms, so
added in their config.
Signed-off-by: Shaveta Leekha <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
[York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs]
Reviewed-by: York Sun <[email protected]>
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When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <[email protected]>
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Add a new serdes2 protocol 0x27.
Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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