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2025-03-24Merge tag 'v2025.04-rc5' into nextTom Rini
Prepare v2025.04-rc5
2025-03-18Merge patch series "pxe: Precursor series for supporting read_all() in ↵Tom Rini
extlinux / PXE" Simon Glass <[email protected]> says: This series includes some patches related to allowing read_all() to be used with the extlinux / PXE bootmeths. These patches were split out from the stb4 series, since it will need to have additional patches for LWIP, to avoid breaking PXE booting when LWIP is used. Link: https://lore.kernel.org/r/[email protected]
2025-03-18boot: arm: riscv: sandbox: Add a format for the booti fileSimon Glass
Arm invented a new format for arm64 and something similar is also used with RISC-V. Add this to the list of supported formats and provide a way for the format to be detected on both architectures. Update the genimg_get_format() function to support this. Fix up switch() statements which don't currently mention this format. Booti does not support a ramdisk, so this can be ignored. Signed-off-by: Simon Glass <[email protected]>
2025-03-17arm: riscv: efi: Export _start symbol from crt0_*_efi stubsSam Edwards
While the _start label is only intended for use locally to populate the (hand-written) PE header, the linker script includes ENTRY(_start) which designates it as the entry point in the output ELF, resulting in linker warnings under some linkers (e.g. LLVM's lld) due to _start not being a globally-visible symbol. Since ELF is only an intermediary build format, and the aforementioned PE header correctly points to _start, the ENTRY(_start) directive could easily be removed to silence this warning. However, since some developers who are debugging EFI by analyzing the intermediary ELF may appreciate having correct entry-point information, this patch instead promotes the _start labels to global symbols, silencing the linker warning and making the intermediary ELF reflect the true entry point. This patch doesn't affect the final output binaries in any way. Signed-off-by: Sam Edwards <[email protected]>
2025-03-14treewide: Add a function to change page permissionsIlias Apalodimas
For armv8 we are adding proper page permissions for the relocated U-Boot binary. Add a weak function that can be used across architectures to change the page permissions Tested-by: Neil Armstrong <[email protected]> # on AML-S905X-CC Signed-off-by: Ilias Apalodimas <[email protected]>
2025-03-10usb: gadget: Remove final remnants of CONFIG_USB_DEVICETom Rini
The lone user of the legacy USB device framework have been removed for some time. Remove the final parts of the code that were missed. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Mattijs Korpershoek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mattijs Korpershoek <[email protected]>
2025-01-17efi_loader: correct SizeOfCode, SizeOfInitializedDataHeinrich Schuchardt
The fields SizeOfCode, SizeOfInitializedData, and SizeOfUninitializedData are define in the PE-COFF specification [1]. * SizeOfCode must match the size of all .text sections. * SizeOfInitializedData must match the size of all .data sections. * SizeOfUninitializedData must match the size of all .bss sections. We only have one .text and one .data section. SizeOfCode and SizeOfInitializedData have to be calculated as the difference between the end and the start of the respective section. As we don't have any .bss sections in the generated EFI binaries. SizeOfUninitializedData must remain 0. [1] https://learn.microsoft.com/en-us/windows/win32/debug/pe-format Reviewed-by: Ilias Apalodimas <[email protected]> Signed-off-by: Heinrich Schuchardt <[email protected]>
2025-01-17efi_loader: use INCLUDE in EFI linker scriptsHeinrich Schuchardt
Except for the architecture specific lines ARM and RISC-V can use the same linker script. Move the common lines to an include. Reviewed-by: Ilias Apalodimas <[email protected]> Signed-off-by: Heinrich Schuchardt <[email protected]>
2025-01-16riscv: Fallback to riscv,isaMayuresh Chitale
Update the cpu probing to fallback to "riscv,isa" property if "riscv,isa-extensions" is not available and modify the riscv CMO code to use the block size that was probed during cpu setup. Signed-off-by: Mayuresh Chitale <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2024-11-24dm: Add dm_remove_devices_active() for ordered device removalJanne Grunau
This replaces dm_remove_devices_flags() calls in all boot implementations to ensure non vital devices are consistently removed first. All boot implementation except arch/arm/lib/bootm.c currently just call dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL). This can result in crashes when dependencies between devices exists. The driver model's design document describes DM_FLAG_VITAL as "indicates that the device is 'vital' to the operation of other devices". Device removal at boot should follow this. Instead of adding dm_remove_devices_flags() with (DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL) everywhere add dm_remove_devices_active() which does this. Fixes a NULL pointer deref in the apple dart IOMMU driver during EFI boot. The xhci-pci (driver which depends on the IOMMU to work) removes its mapping on removal. This explodes when the IOMMU device was removed first. dm_remove_devices_flags() is kept since it is used for testing of device_remove() calls in dm. Signed-off-by: Janne Grunau <[email protected]>
2024-10-29riscv: resume needs to be a globalAnton Blanchard
If we take an exception before u-boot is relocated, there's a good chance we will end up in an endless loop of exceptions because resume is invalid until after relocation. Signed-off-by: Anton Blanchard <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2024-10-28riscv: cache: Add CBO instructionsMayuresh Chitale
Define CBO inval and flush instructions and use those for the dcache inval and flush operations respectively. Signed-off-by: Mayuresh Chitale <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2024-10-28riscv: add missing linefeed in error messageHeinrich Schuchardt
* Messages written with log_err() should be terminated with linefeed. * Spell device-tree with hyphen as elsewhere in U-Boot. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2024-10-11Merge patch series "Tidy up use of 'SPL' and CONFIG_SPL_BUILD"Tom Rini
Simon Glass <[email protected]> says: When the SPL build-phase was first created it was designed to solve a particular problem (the need to init SDRAM so that U-Boot proper could be loaded). It has since expanded to become an important part of U-Boot, with three phases now present: TPL, VPL and SPL Due to this history, the term 'SPL' is used to mean both a particular phase (the one before U-Boot proper) and all the non-proper phases. This has become confusing. For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL' phases, not just SPL. So code which can only be compiled for actual SPL, for example, must use something like this: #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) In Makefiles we have similar issues. SPL_ has been used as a variable which expands to either SPL_ or nothing, to chose between options like CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was updated to support 'VPL_' as well. This series starts a change in terminology and usage to resolve the above issues: - The word 'xPL' is used instead of 'SPL' to mean a non-proper build - A new CONFIG_XPL_BUILD define indicates that the current build is an 'xPL' build - The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now defined for TPL and VPL phases - The existing SPL_ Makefile variable is renamed to SPL_ - The existing SPL_TPL Makefile variable is renamed to PHASE_ It should be noted that xpl_phase() can generally be used instead of the above CONFIGs without a code-space or run-time penalty. This series does not attempt to convert all of U-Boot to use this new terminology but it makes a start. In particular, renaming spl.h and common/spl seems like a bridge too far at this point. The series is fully bisectable. It has also been checked to ensure there are no code-size changes on any commit.
2024-10-11global: Rename SPL_TPL_ to PHASE_Simon Glass
Use PHASE_ as the symbol to select a particular XPL build. This means that SPL_TPL_ is no-longer set. Update the comment in bootstage to refer to this symbol, instead of SPL_ Signed-off-by: Simon Glass <[email protected]>
2024-10-11global: Rename SPL_ to XPL_Simon Glass
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is no-longer set. Signed-off-by: Simon Glass <[email protected]>
2024-10-11arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <[email protected]>
2024-10-09efi: arm: x86: riscv: Drop crt0/relocal extra- rulesSimon Glass
The link rule (for $(obj)/%_efi.so) in scripts/Makefile.lib handles pulling in efi_crt0.o and efi_reloc.o so drop the 'extra' rules. Signed-off-by: Simon Glass <[email protected]> Suggested-by: Heinrich Schuchardt <[email protected]>
2024-10-09efi_loader: Rename and move CMD_BOOTEFI_HELLO_COMPILESimon Glass
This is not actually a command so the name is confusing. Use BOOTEFI_HELLO_COMPILE instead. Put it in the efi_loader directory with the other such config options. The link rule (for $(obj)/%_efi.so) in scripts/Makefile.lib handles pulling in efi_crt0.o and efi_reloc.o so drop the 'extra' rules. Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Ilias Apalodimas <[email protected]>
2024-09-16Merge tag 'v2024.10-rc5' into nextTom Rini
Prepare v2024.10-rc5
2024-09-10riscv: allow to enable SHOW_REGS in main U-Boot onlyHeinrich Schuchardt
To minimize SPL size it is reasonable to disable SHOW_REGS. For main U-Boot the size restrictions are much more relaxed. * Provide separate Kconfig symbols for SPL and main U-Boot. * Add a help text. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2024-09-03lmb: do away with arch_lmb_reserve()Sughosh Ganu
All of the current definitions of arch_lmb_reserve() are doing the same thing -- reserve the region of memory occupied by U-Boot, starting from the current stack address to the ram_top. Introduce a function lmb_reserve_uboot_region() which does this, and do away with the arch_lmb_reserve() function. Instead of using the current value of stack pointer for starting the reserved region, have a fixed value, considering the stack size config value. Signed-off-by: Sughosh Ganu <[email protected]> Reviewed-by: Simon Glass <[email protected]> Acked-by: Ilias Apalodimas <[email protected]>
2024-09-03lmb: make LMB memory map persistent and globalSughosh Ganu
The current LMB API's for allocating and reserving memory use a per-caller based memory view. Memory allocated by a caller can then be overwritten by another caller. Make these allocations and reservations persistent using the alloced list data structure. Two alloced lists are declared -- one for the available(free) memory, and one for the used memory. Once full, the list can then be extended at runtime. [sjg: Use a stack to store pointer of lmb struct when running lmb tests] Signed-off-by: Sughosh Ganu <[email protected]> Signed-off-by: Simon Glass <[email protected]> [sjg: Optimise the logic to add a region in lmb_add_region_flags()]
2024-07-22riscv: semihosting: correct alignmentHeinrich Schuchardt
Commit 7400d34ba992 ("riscv: semihosting: replace inline assembly with assembly file") reduced the alignment of function smh_trap(). As described in the "RISC-V Semihosting" specification [1] the ssli, ebreak, and srai statements must all reside in the same memory page. [1] RISC-V Semihosting, Version 0.4, 12th June 2024 https://github.com/riscv-non-isa/riscv-semihosting Fixes: 7400d34ba992 ("riscv: semihosting: replace inline assembly with assembly file") Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2024-07-22riscv: add RISC-V fields to bdinfo commandHeinrich Schuchardt
The firmware invoking main U-Boot uses * a0 to pass the boot hart * a1 to pass a device-tree Let the bdinfo command print this information, e.g. boot hart = 0x000000000000001b firmware fdt= 0x0000000087e00000 The firmware fdt field will only be printed if it is non-zero. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2024-05-14riscv: simplify backtrace reportHeinrich Schuchardt
* We already have a header 'backtrace', there is no need to repeat the word backtrace on every line. * Add a blank line before the backtrace section of the crash report for improved readability. * If U-Boot is compiled without backtrace, there is no need to write a message at all. * Avoid #ifdef. We prefer functions to always be compiled and let the linker remove them if not needed. * Foresee 3 digits for the backtrace index. For testing the 'exception' command can be used. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2024-05-06global: Make <asm/global_data.h> include <asm/u-boot.h>Tom Rini
This follows the example of RISC-V where <asm/global_data.h> includes <asm/u-boot.h> directly as "gd" includes a reference to bd_info already and so the first must include the second anyhow. We then remove <asm/u-boot.h> from all of the places which include references to "gd" an so have <asm/global_data.h> already. Signed-off-by: Tom Rini <[email protected]>
2024-04-18Revert "Merge patch series "pxe: Allow extlinux booting without CMDLINE ↵Tom Rini
enabled"" As reported by Jonas Karlman this series breaks booting on some AArch64 platforms with common use cases. For now the best path forward is to revert the series. This reverts commit 777c28460947371ada40868dc994dfe8537d7115, reversing changes made to ab3453e7b12daef47b9e91da2a2a3d48615dc6fc. Link: https://lore.kernel.org/u-boot/[email protected]/ Signed-off-by: Tom Rini <[email protected]>
2024-04-10Merge patch series "pxe: Allow extlinux booting without CMDLINE enabled"Tom Rini
Simon Glass <[email protected]> says: This series is the culmanation of the current line of refactoring series. It adjusts pxe to call the booting functionality directly rather than going through the command-line interface. With this is is possible to boot using the extlinux bootmeth without the command line enabled. It also updates fastboot to do a similar thing.
2024-04-10treewide: Make arch-specific bootm code depend on BOOTMSimon Glass
Allow these functions to be compiled in when CONFIG_BOOTM is enabled, even if CONFIG_CMD_BOOTM is not. Signed-off-by: Simon Glass <[email protected]> Acked-by: Angelo Dureghello <[email protected]>
2024-04-09riscv: add backtrace supportBen Dooks
When debugging, it is useful to have a backtrace to find out what is in the call stack as the previous function (RA) may not have been the culprit. Since this adds size to the build, do not add it by default and avoid putting it in the SPL build if not needed. Signed-off-by: Ben Dooks <[email protected]> Tested-by: Leo Yu-Chi Liang <[email protected]>
2024-02-28efi_loader: set IMAGE_DLLCHARACTERISTICS_NX_COMPATHeinrich Schuchardt
The IMAGE_DLLCHARACTERISTICS_NX_COMPAT flag marks an EFI binary where the following conditions are met [1]: * Executable and writable sections are separated. * The application does not run self-modifying code. * The application uses the EFI_MEMORY_ATTRIBUTE_PROTOCOL when loading executable code. * The application does not assume that all memory ranges are usable. * The stack is not expected to be executable. The only EFI binaries U-Boot provides that do not fulfill these requirements are the EFI app and the EFI payload. Once we have implemented separation of writable and executable memory in U-Boot we can use the IMAGE_DLLCHARACTERISTICS_NX_COMPAT flag to decide if we will load an EFI binary. [1] New UEFI CA memory mitigation requirements for signing https://techcommunity.microsoft.com/t5/hardware-dev-center/new-uefi-ca-memory-mitigation-requirements-for-signing/ba-p/3608714 Signed-off-by: Heinrich Schuchardt <[email protected]>
2024-01-29riscv: separate .data and .text sections of EFI binariesHeinrich Schuchardt
EFI binaries should not contain sections that are both writable and executable. Separate the RX .text section from the RW .data section Signed-off-by: Heinrich Schuchardt <[email protected]>
2024-01-29riscv: page align EFI binary sectionHeinrich Schuchardt
Change the alignment of the relocation code in EFI binaries to match page boundaries. Signed-off-by: Heinrich Schuchardt <[email protected]>
2024-01-29riscv: conflicting SPDX license linker scriptsHeinrich Schuchardt
Fix conflicting SPDX license information in linker scripts introduced by commit 7215787c4ea4 ("SPDX: Convert single license tags to Linux Kernel style"). Fixes: 7215787c4ea4 ("SPDX: Convert single license tags to Linux Kernel style") Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2023-12-27riscv: cache: support cache enable in SPL stageZong Li
The power gating feature of pl2 should be enabled as early as possible, it would be better to put it in SPL stage. Signed-off-by: Zong Li <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2023-12-21Merge patch series "Complete decoupling of bootm logic from commands"Tom Rini
Simon Glass <[email protected]> says: This series continues refactoring the bootm code to allow it to be used with CONFIG_COMMAND disabled. The OS-handling code is refactored and a new bootm_run() function is created to run through the bootm stages. This completes the work. A booti_go() function is created also, in case it proves useful, but at last for now standard boot does not use this. This is cmdd (part d of CMDLINE refactoring) It depends on dm/bootstda-working which depends on dm/cmdc-working
2023-12-21bootm: Adjust arguments of boot_os_fnSimon Glass
Adjust boot_os_fn to use struct bootm_info instead of the separate argc, argv and image parameters. Update the handlers accordingly. Few of the functions make use of the arguments, so this improves code size slightly. Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2023-12-21riscv: Add a reset_cpu() functionSimon Glass
The current do_reset() is called from a command context. Add a function which can be used from anywhere, as is done on ARM. Adjust do_reset() to call it. Note that reset_cpu() is normally provided by SYSRESET so make this declaration conditional on that being disabled. Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Chanho Park <[email protected]> Tested-by: Chanho Park <[email protected]>
2023-12-06riscv: andes: Fix enable register settings of PLICSWYu Chien Peter Lin
On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <[email protected]> Reviewed-by: Randolph <[email protected]>
2023-11-02riscv: allow resume after exceptionHeinrich Schuchardt
If CSRs like seed are readable by S-mode, may not be determinable by S-mode. For safe driver probing allow to resume via a longjmp after an exception. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2023-11-02riscv: Weakly define invalidate_icache_range()Samuel Holland
Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2023-10-24riscv: Remove common.h usageTom Rini
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Rick Chen <[email protected]>
2023-10-19riscv: Add Zbb support for building U-BootYu Chien Peter Lin
This patch adds ISA string to the -march to generate zbb instructions for U-Boot binaries, along with optimized string functions introduced from Linux kernel. Signed-off-by: Yu Chien Peter Lin <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2023-10-19riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategyRandolph
Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2023-10-04riscv: bootstage: correct bootstage_report guardChanho Park
Below warning can be occurred when CONFIG_BOOTSTAGE and !CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED for SPL build. arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of function 'bootstage_report' 46 | bootstage_report(); | ^~~~~~~~~~~~~~~~ | bootstage_error Signed-off-by: Chanho Park <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2023-10-02Merge branch 'next'Tom Rini
Signed-off-by: Tom Rini <[email protected]>
2023-09-24common: Drop linux/printk.h from common headerSimon Glass
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <[email protected]>