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Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board)
Signed-off-by: Miao Yan <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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Re-write the logic in qemu_fwcfg_list_firmware(), add a function
qemu_fwcfg_read_firmware_list() to handle reading firmware list.
Signed-off-by: Miao Yan <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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This patch adds a parameter to the function setup_early_uart() to either
enable or disable the internal BayTrail legacy UART. Since the name
setup_early_uart() does not match its functionality any more, lets
rename it to setup_internal_uart() as well in this patch.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Until we have a proper video uclass we can use syscon to handle the GMA
device, and avoid the special device tree and PCI searching. Update the code
to work this way.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Each system controller can have a number to identify it. It can then be
accessed using syscon_get_by_driver_data(). Put this in a shared header
file and update the only current user.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This is not used on link which is the only ivybridge board. Drop this code.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This is not needed. On reset wake-on-disconnect is already set. It may a
problem during a soft reset or resume, but for now it does not seem
important. Also drop the command register update since PCI auto-config
does it for us.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This function is called all over the place. Convert it use the driver model
PCI API, and rationalise the calls.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This code relates to the PCH, so we should move it into the same file.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Convert this file to use the driver model PCI API.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Convert these functions to use the driver model PCI API.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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SDRAM init needs access to the Northbridge controller and the Intel
Management Engine device. Add the latter to the device tree and convert all
of this code to driver model.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Drop the lpc_init_extra() function and just use the post-relocation LPC
probe() instead.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This graphics init code is best placed in the gma init code. Move the code
and drop the function.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Instead of manually initing the device, probe the SATA device and move the
init there.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This function does nothing now so can be dropped.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relocation. This can do the early setup.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Adjust most of the remaining functions in this file to use the driver model
PCI API. The one remaining function is bridge_silicon_revision() which will
need a little more work.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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There are no other implementations of this function, and boards that need it
can implement a CPU driver.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Use the CPU driver's probe() method to perform the CPU init. This will happen
automatically when the first CPU is probed.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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In preparation for adding an init() method to the LPC uclass, rename this
existing function so that it will not conflict.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove
this in a later patch.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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There are no callers now. Platforms which need to set up interrupts their
own way can implement an interrupt driver. Drop this function.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Most x86 interrupt drivers will want to use the standard PIRQ routing and
table setup. Put this code in a common function so it can be used by those
drivers that want it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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At present interrupt routing is set up from arch_misc_init(). We can do it
a little later instead, in interrupt_init().
This removes the manual pirq_init() call. Where the platform does not have
an interrupt router defined in its device tree, no error is generated. Some
platforms do not have this.
Drop pirq_init() since it is no-longer used.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.
Signed-off-by: Tom Rini <[email protected]>
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The QEMU fw_cfg interface allows the guest to retrieve various data
information from QEMU. For example, APCI/SMBios tables, number of online
cpus, kernel data and command line, etc.
This patch adds support for QEMU fw_cfg interface.
Signed-off-by: Miao Yan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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Add several macros for LPC decode registers on PCH.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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fsp_init() runtime buffer parameter might be different across
different platforms. Move this to update_fsp_configs().
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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All FSP spec v1.0 complaint FSP binary uses struct fspinit_rtbuf
as defined by the 1.0 spec, however there are FSPs that does not
follow 1.0 spec (possible due to that FSP predates the 1.0 spec),
and future FSP binary that is complaint to v1.1 spec defines an
optional paltform-specific runtime data in the struct fspinit_rtbuf.
Hence move the definition to chipset header.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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To support platform-specific configurations (might not always be
UPD on some platform), use a better name update_fsp_configs() and
accepct struct fsp_config_data as its parameter so that platform
codes can handle whatever configuration data for that FSP.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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FSP has several config data like UPD, HDA verb table which can be
overridden or provided by bootloader. Currently in U-Boot only UPD
is handled via struct shared_data. To accommodate any platform, we
rename shared_data to fsp_config_data and move the definition from
common place fsp_support.h to platform-specific place fsp_configs.h.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Save boot_mode in struct shared_data for future refactoring.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Declare stack_top as u32 in struct shared_data and struct common_buf
so that we can avoid casting in fsp_init().
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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There is no need to pass shared_data to fsp_continue() so we can
remove unnecessary codes that simplifies the function a lot.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Use the driver-model PCI functions here where possible. For now we have to
search for the device with pci_bus_find_bdf() but at some point we can put
this in a proper driver and avoid this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Now that we have converted all x86 boards to use driver model timer,
remove these legacy timer codes in the tsc driver.
Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option,
as it is not needed with driver model.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This is not referenced anywhere. Remove it, as well as
tsc_base_kclocks and tsc_prev in the global data.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Fix 'Reomve' typo:
Signed-off-by: Simon Glass <[email protected]>
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Now that we have converted all x86 boards to use driver model pci,
remove these legacy pci codes.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA display controller
class in the PCI configuration space, and should also prevent
it from responding to VGA legacy memory range and I/O addresses.
However test result shows that with just VGA Disable bit set and
a PCIe graphics card connected to one of the PCIe controllers on
the E6xx, accessing the VGA legacy space still causes system hang.
After a number of attempts, it turns out besides VGA Disable bit,
the SDVO (D3:F0) device should be disabled to make it work.
To simplify, use the Function Disable register (offset 0xc4)
to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
two devices will be completely disabled (invisible in the PCI
configuration space) unless a system reset is performed.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c,
to match their header file names (i8254.h and i8259.h).
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This cleans up i8254 and i8259 codes to fix several cosmetic
issues, like coding convention and some comments improvement.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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CONFIG_SYS_NUM_IRQS is actually not something we can configure,
but an architecture defined number of ISA IRQs. Move it from
x86-common.h to asm/interrupt.h and rename it to SYS_NUM_IRQS.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Use the generic bitops and also add custom __ffs() implementation
as per the kernel.
Also align the ffs() implementation with the kernel.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Currently struct fmap_entry is used to describe a mrc region.
However this structure contains some other fields that are not
related to mrc cache and causes confusion. Besides, it does not
include a base address field to store SPI flash's base address.
Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to
calculate the SPI flash base address, which unfortunately is
not 100% correct as CONFIG_ROM_SIZE may not match the whole
SPI flash size.
Define a new struct mrc_region and use it instead.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This adds mrccache_reserve(), mrccache_get_region() and
mrccache_save() APIs to the mrccache codes. They are ported
from the ivybridge implementation, but with some changes.
For example, in the mrccache_reserve(), ivybridge version
only reserves the pure MRC data, which causes additional
malloc() when saving the cache as the save API needs some
meta data. Now we change it to save the whole MRC date plus
the meta data to elinimate the need for the malloc() later.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Fix some nits, improve some comments and reorder some codes
a little bit.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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