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The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on
P1022/P1013 SoCs.
Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2.
Signed-off-by: Jiang Yutang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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The MMC registers are accessed through struct s5p_mmc member
variables. MMC controller "control4" register offset is set
to 0x8C as per data sheet. The size of struct s5p_mmc is also
corrected.
Signed-off-by: Chander Kashyap <[email protected]>
Signed-off-by: Tushar Behera <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Use the global data instead of bss variable, replace as follow.
count_value -> removed
timestamp -> tbl
lastdec -> lastinc
Signed-off-by: Minkyu Kang <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Acked-by: Albert ARIBAUD <[email protected]>
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Use pwm functions for timer that is PWM timer 4.
Signed-off-by: Minkyu Kang <[email protected]>
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This is common pwm driver of S5P.
Signed-off-by: Donghwa Lee <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Since nand boot have some limit for the first 4KB, We only
disable the LED function to reduce the code space. At the
same time, Fix the compile error for LED function undefined
in the compile time of nand_spl.
Signed-off-by: Zhong Hongbo <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Monitor protection region in FLASH did not cover .rel.dyn
and .dynsym sections, because it uses __bss_start to compute
monitor_flash_len. Use _end instead.
Add _end to linker scripts for end of u-boot image
Add _end_ofs to all the start.S.
Signed-off-by: Po-Yu Chuang <[email protected]>
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Currently, _end is used for end of BSS section. We want _end to mean
end of u-boot image, so we rename _end to __bss_end__ first.
Signed-off-by: Po-Yu Chuang <[email protected]>
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The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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To recognize DIMMs with ECC capability by testing ECC bit only. Not to be
confused by Address Parity bit.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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commit 8aba9dceebb14144e07d19593111ee3a999c37fc
Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS
breaks the usage of --gc-section to build nand_spl. We still need linker option
--gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes
the --gc-sections to each uboot image.
To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace
PLATFORM_LDFLAGS in the Makefile of each nand_spl board.
Signed-off-by: Scott Wood <[email protected]>
Signed-off-by: Haiying Wang <[email protected]>
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The start.o section is changed by --gc-section option of ld.
Of this using KEEP order, therefore, evade this problem.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Some board of SH does not have flash memoy.
This revises it to initialize Flash when CONFIG_SYS_NO_FLASH is not
defined.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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There is a small ordering issue in the master core in that we need to
make sure the disabling of the timebase in the SoC is visible before we
set the value to 0. We can simply just read back the value to
synchronizatize the write, before we set TB to 0.
Reported-by: Dan Hettena
Tested-by: Dan Hettena
Signed-off-by: Kumar Gala <[email protected]>
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The POST word is stored in a spare register in the PIC on MPC8[5/6]xx
processors. When interrupt_init() is called, this register gets reset
which resulted in all POST_RAM POSTs not being ran due to the corrupted
POST word. To resolve this, store off POST word before the PIC is
reset, and restore it after the PIC has been initialized.
Signed-off-by: John Schmoller <[email protected]>
Signed-off-by: Peter Tyser <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Copying directly from ECM/PQ3 is not correct for how CoreNet based
platforms handle boot page translation.
Signed-off-by: Ed Swarthout <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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This commit updates the mach-types based on the latest
in linus's head
Signed-off-by: Sandeep Paulraj <[email protected]>
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Signed-off-by: Fabio Estevam <[email protected]>
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Signed-off-by: Fabio Estevam <[email protected]>
Signed-off-by: Magnus Lilja <[email protected]>
Tested-by: Magnus Lilja <[email protected]>
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get_sp() was incorrectly excluded if none of
CONFIG_SETUP_MEMORY_TAGS
CONFIG_CMDLINE_TAG
CONFIG_INITRD_TAG
CONFIG_SERIAL_TAG
CONFIG_REVISION_TAG
were defined.
Signed-off-by: Po-Yu Chuang <[email protected]>
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This patch adds the Multiple Function Pin configuration support for
Marvell PANTHEON SoCs
Signed-off-by: Lei Wen <[email protected]>
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Pantheon Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref:
http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf
SoC versions Supported:
1) PANTHEON920 (TD)
2) PANTHEON910 (TTC)
Signed-off-by: Lei Wen <[email protected]>
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Since there are lots of difference between kirkwood and armada series,
it is better to seperate them but still keep the most common file
shared by all marvell platform in the mv-common configure file.
This patch move the kirkwood only driver definitoin in mv-common to
the <soc_name>/config.h.
This patch is tested with compilation for armada100 and guruplug.
Signed-off-by: Lei Wen <[email protected]>
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Commit 3c0659b "ARM: Avoid compiler optimization for readb, writeb
and friends." introduced I/O accessors with memory barriers.
Unfortunately the new write*() accessors introduced a bug:
The problem is that the argument "v" gets evaluated twice. This
breaks code like used here (from "drivers/net/dnet.c"):
for (i = 0; i < wrsz; i++)
writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
Use auxiliary variables to avoid such problems.
Signed-off-by: Wolfgang Denk <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Alexander Holler <[email protected]>
Cc: Dirk Behme <[email protected]>
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Signed-off-by: Alexander Stein <[email protected]>
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Signed-off-by: Tom Warren <[email protected]>
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Fix ancient code which worked with MSR in a bad way.
Use rtid instruction which enable IRQs and jump.
Signed-off-by: Michal Simek <[email protected]>
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u-boot BSP generates XILINX_USE_MSR_INSTR macro
even for system with MSR=0. That's why explicitly
check that MSR=1.
Signed-off-by: Michal Simek <[email protected]>
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x86 has always used relocation offset in the opposite sense to the ELF
standard - Fix this
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In later patches, cpu_init_f will be called before console has been
initialised and printf will not be legitimately available
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