| Age | Commit message (Collapse) | Author |
|---|
|
https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/24816
Please pull the SoCFPGA changes for next from u-boot-socfpga, containing
boot support for the Altera SoCFPGA Agilex 5 platform in U-Boot. The
changes include:
1. Board-specific configurations and setup required to enable Agilex 5
operation in U-Boot.
2. Integration of cache coherency unit (CCU) initialization routine,
including CCU conguration in DT.
3. Clock, firewall (configured in DT), SMMU, low level initialization
specific to Agilex 5.
4. Integration of memory initialization routine, including DDR setup.
This patch set has been tested on Agilex 5 devkit with QSPI boot
(UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
|
|
Add board_boot_order() to retrieve the list of boot devices from
spl-boot-order property in device tree. This board_boot_order()
would be used for all Intel SOC64 devices.
Signed-off-by: Tien Fong Chee <[email protected]>
|
|
Introduce a new symbol in the beginning of .data section in
the common ARMv8 linker script and use that as a reference
for data save and restore.
Previously, the code would rely on calculating the start of
the .data section address via data size, however, we observed
that the data size does not really reflect the SPL mapped
addresses.
In our case, the binman_sym section size was not included in
the data size, which will result in a wrong address for the
.data start section, which prevents us from properly saving
and restoring SPL data.
This approach skips the calculation for the starting address
of the .data section, and instead just defines the beginning
address of the .data section and calling the symbol as needed,
in which we think as a simpler and much more robust method.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Add SPL support for Agilex5 SoCFPGA.
Signed-off-by: Tien Fong Chee <[email protected]>
|
|
Adding DDR driver support for Agilex5 series.
Signed-off-by: Tingting Meng <[email protected]>
|
|
As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.
Signed-off-by: Mahesh Rao <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Board ID is exported as environment variable for use to boot Linux with FIT
configuration.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Update the print info per Agilex5
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Allow non-secure accesses only with SMMU peripherals. This would protect
the content in DDR secure region from accidentally modified by SMMU
peripherals.
Signed-off-by: Tien Fong Chee <[email protected]>
|
|
set/way instructions "dc cisw" which is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.
Signed-off-by: Tien Fong Chee <[email protected]>
|
|
Enable PSCI reset driver for Agilex5 cold and warm reset
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Enable XGMAC for SoCFPGA Agilex5 devkit.
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Tien Fong Chee <[email protected]>
|
|
These firewall configure settings are needed to disable firewall on
respective hardware component so both secure and non-secure transactions
are allowed.
Signed-off-by: Tien Fong Chee <[email protected]>
|
|
These configuration settings are required to enable cache maintenance and
access between initiators and targets.
Signed-off-by: Tien Fong Chee <[email protected]>
|
|
Agilex5 supports both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and Agilex5 device.
Signed-off-by: Tien Fong Chee <[email protected]>
|
|
Status polling is used instead of using interrupt controller for Agilex5.
Disabling GICV3 in Agilex5 target, as well as disabling GICV2 enabled by
default for all SoCFPGA devices.
All the other SoCFPGA devices uses GICV2, thus enabling GICV2 in each of
the devices.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
There are 5 L4 watchdogs and one SDM triggered warm reset bit
in Agilex5 reset manager "stat" register where bit 16:20 for L4
watchdogs. Assigning value 1 to these bits in the register address
will initiate SDM to trigger warm reset.
Introducing new warm reset mask for Agilex5 to trigger warm reset
to all five L4 watchdogs.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Agilex5 retrieves its clock manager address via probing its own clock
driver model during SPL initialization.
Therefore, excluding Agilex5 from calling generic clock driver in misc
driver.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
|
|
Initial creation of new system manager driver.
Add supports for the SOCFPGA System Manager Register block which
aggregates different peripheral function into one area.
On 64 bit ARM parts, the system manager only can be accessed during
EL3 mode, this driver model provide user the high level access
to system register and abstract user from low level access.
The base address of system manager can be retrieved
using DT framework through the System Manager driver.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Boon Khai Ng <[email protected]>
|
|
Enable i2c3 node in Agilex5 device tree
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
|
|
Prepare v2025.04-rc3
|
|
Branch contains bringup of Acer Iconia Tab A500 (codename picasso), a
Tegra 2 Android device with decent Linux kernel support. Ondevice tests
and U-Boot test suit all passed.
|
|
Defining CONFIG_MT8512 is unnecessary as now board for mediatek
target can be changed in config.
Use CONFIG_TARGET_MT8512 to replace CONFIG_MT8512.
Signed-off-by: Weijie Gao <[email protected]>
|
|
Not all MediaTek platforms needs u-boot-mtk.bin.
This patch will let u-boot generates u-boot-mtk.bin only if
CONFIG_MTK_BROM_HEADER_INFO is not empty.
Signed-off-by: Weijie Gao <[email protected]>
|
|
Tom Rini <[email protected]> says:
This small series separates "bloblist" and "standard passage" to allow
for these similar concepts to explore solutions to problems without
introduces breaking changes to the other.
Link: https://lore.kernel.org/r/[email protected]
|
|
Refactor the xferlist to remove the relocating when bloblist passed
from the boot args.
Refactor bloblist init to use incoming standard passage by default
if a valid transfer list exists in the boot args.
For bloblist relocation, use the actual total size if it has a smaller
BLOBLIST_SIZE_RELOC.
Signed-off-by: Raymond Mao <[email protected]>
Suggested-by: Ilias Apalodimas <[email protected]>
|
|
The device tree for rk3036 combined is now
available in the /dts/upstream directory.
Use imply OF_UPSTREAM to migrate all rk3036 boards.
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Johan Jonker <[email protected]>
|
|
Most Rockchip SoCs use 0x0 as DRAM base address, however some SoCs use
0x60000000 and RK3576 use 0x40000000 as DRAM base address.
CFG_SYS_SDRAM_BASE is defined with correct address for each SoC and
U-Boot proper use this to set correct gd->ram_base in setup_dest_addr().
SPL never assign any value to gd->ram_base and instead use the default,
0x0. Set correct gd->ram_base in dram_init() to ensure its correctness
in SPL.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
U-Boot only works correctly when it uses RAM below the 4G address
boundary on Rockchip SoCs. Limit usable gd->ram_top to max 4G.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
Allow the first bank to extend beyond 4 GiB when the blob of space for
peripheral is located before start of DRAM, e.g. when start of DRAM
is 0x40000000 and continue beyond the 4 GiB mark.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
In the GRF header file, some instances of UART2 pinmux are prefixed with
"GRF_UART2DBG" while others have "GRF_UART2DGB".
Since UART2 is the default console UART and used for debugging, it is
more likely the name should be UART2DBG.
Fix the ones that are wrong.
Fixes: a2c08df3813b ("pinctrl: add driver for rk3399")
Fixes: fa72de10452c ("rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h")
Signed-off-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Paul Kocialkowski <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
These power rails must be on very early for the U-Boos TPL banner to be
show over debug UART.
This reverts commit 4576e65a5d6b10fd207c3a44061676ce0220d794.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
These power rails must be on very early for the U-Boos SPL banner to be
show over debug UART.
This reverts commit af518a1dfe637cb4dc486d7a832585e4a48bc970.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
The PCS exists only in GMAC1 and relates to SGMII interface and
is used to control the SGMII PHY.
Signed-off-by: Jim Liu <[email protected]>
[trini: Adjust slightly for white space and to move 'start' to within if
block]
|
|
https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2025.07 cycle:
This feature set includes improvements on the atmel-quadspi driver, a
fix for the nand driver, and improvements on the pinctrl driver to be
able to use the Linux DT (also sync on the DT side as well).
|
|
The Acer Iconia A500 is a tablet computer designed, developed and
marketed by Acer Inc. It is powered by 1 GHz Nvidia Tegra 2 processor
and 1GB DDR2 RAM. The A500 is sold with 64 GB, although both 16 GB
and 32 GB models are available.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
|
|
Add empty weak assembler function armv8_switch_to_el2_prep() which is
jumped to just before U-Boot determines which EL it is running in and
decides which path to take to boot the Linux kernel.
This weak function is meant to be used by architecture specific code
to implement jump to a firmware blob, which then returns right past
this weak function and continues execution of U-Boot code which then
boots the Linux kernel. One example of such use case is when U-Boot
jump tp TFA BL31, which switches from EL3 to EL2 and then returns to
U-Boot code newly running in EL2 and starts the Linux kernel.
The weak function is called with caches already disabled and DM shut
down. Any preparatory work or even loading of more data must be done
in board_prep_linux(), this hook is meant only for the final jump to
the firmware and return to U-Boot before booting Linux.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
|
|
Judith Mendez <[email protected]> says:
Some K3 devices like am62x and am64x have a M4 processor in the MCU
voltage domain. This patch series introduces remoteproc M4 driver which
will be used to load firmware into and start the M4 remote core.
This series also adds support for R5F cores on am64x SoCs in patch 2 and
sets up environment to load FW in remote cores in patch 3,4,5.
This patch series also enables remoteproc drivers by default as per what
remoteproc sybsystem is supported per SoC, thus all remoteproc options
are now deleted in configs/* since they are no longer required.
This patch series was tested on am64x EVM, am62x SK, am62ax SK,
am62px SK boards.
Any additional tested by's are welcome since I was not able to
test any additional boards.
Tested by running the following commands in u-boot prompt:
=> setenv dorprocboot 1
=> run boot_rprocs
Link: https://lore.kernel.org/r/[email protected]
|
|
Add remoteproc config options to enable remoteproc drivers by
default as per what remotproc subsystem is supported on each
SoC.
Signed-off-by: Judith Mendez <[email protected]>
|
|
Same as on previous SoC generations this is required for proper
video output work.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
|
|
Bind missing DSI and MIPI calibration devices.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
|
|
Sync DSI nodes with Linux tree.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
|
|
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
|
|
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
|
|
The GPIO banks are added as sub nodes or child nodes under the
pinctrl node (as per Linux ABI) and the reg property which points
to an array of controllers physical base address is removed
to align with the Linux devicetree.
Signed-off-by: Charan Pedumuru <[email protected]>
Signed-off-by: Manikandan Muralidharan <[email protected]>
|
|
Add the missing properties for the pinctrl node and for its
corresponding GPIO bank nodes to align with the Linux DT.
Signed-off-by: Manikandan Muralidharan <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
|
|
Move pinmux nodes defined under the pinctrl node from sam9x60 SoC
DT to its board specific DTS files.
Signed-off-by: Manikandan Muralidharan <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
|
|
Define the pinctrl nodes with its label to align with the Linux DT.
Without this change the pinmux nodes are grouped under an additional
'pinctrl' child node which is not identified by the pinctrl driver
when the GPIO banks are made as child nodes of pinctrl node.
Signed-off-by: Balamanikandan Gunasundar <[email protected]>
Signed-off-by: Manikandan Muralidharan <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
|
|
Add Advanced Interrupt Controller node and define it as interrupt
parent in sam9x60 SoC DT.
Signed-off-by: Manikandan Muralidharan <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20250211:
CI:
- https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/24556
Android:
- Handle boot images with missing DTB
Usb gadget:
- Fix nullptr in g_dnl when serial# is unset
- Add missing schedule() in f_mass_storage gadget
- Add support for STih407 in dwc3-generic
- Fix usb clocks on STih407
- Migrate STih407 to DM_USB_GADGET
|
