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2024-11-27arm64: zynqmp: Also generate images with single DTMichal Simek
Create u-boot-single.itb where only actual DTB is used not really multiple of DTS from OF_LIST. This results in small files without option to change DT. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/9362da506c13382da0c0d41ad8a111d9c1150f08.1732089924.git.michal.simek@amd.com
2024-11-27arm64: zynqmp: Remove mkimage fit scriptMichal Simek
Platform has been switched to binman that's why there is no need for this script and also Kconfig symbols. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/cf438091e43c4c9d535a9cfa2886673aa42a4370.1730452668.git.michal.simek@amd.com
2024-11-27arm64: zynqmp: Generate u-boot.itb and QSPI image via binmanMichal Simek
u-boot.itb has been generated via mkimage_fit_atf.sh but it is on the way out that's why convert it's description to binman. Compare to script binman description is not able to configure BL31 and BL32 load/entry addresses which should be done separately. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/90b613796aee38158252c8bb1dfc3da0420f089d.1730452668.git.michal.simek@amd.com
2024-11-27arm64: zynqmp: Add binman description for SOMMichal Simek
There is necessary to do some steps to compose boot images. These steps were in scripts in layers for a while. That's why introduce description via binman to simplify wiring and remove all scripting around. This should make sure that everybody is up2date with the latest versions. The first step is to create fit image with DTBs with descriptions in configuration node which is written as regular expression to match all SOM versions. Description is there for k24 and k26 in spite of low level psu_init configuration is different. The reason is that it goes to u-boot.itb image which is the same for k24 and k26. u-boot.itb is another image which is generated. It is normally generated via arch/arm/mach-zynqmp/mkimage_fit_atf.sh but this script is supposed to be deprecated. FIT image by purpose is using 64bit addresses to have default option to move images to high DDR (above 4GB). TF-A and TEE are optional components but in the most cases TF-A is present all the time and TEE(OP-TEE) is used by some configurations too. 3rd generated image is boot.bin with updated user field which contains version number. This image can be used with updated Image Selector which supports A/B update mechanisms with rollback protection. 4th image is image.bin which binary file which contains boot.bin and u-boot.itb together and can be programmed via origin Image Selector. This image can be also used for creating one capsule which contains both boot images (in SPL boot flow). Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/35bc47a4a4799c5f5dbea56a45340a2810538330.1730452668.git.michal.simek@amd.com
2024-11-27arm64: zynqmp: Describe empty binman nodeMichal Simek
For enabling binman by default there is a need to have at least empty node present that's why create -u-boot.dtsi with empty node to cover all ZynqMP platforms. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/14d874ad4568fa8e3178e893224fecc5c676f04c.1730452668.git.michal.simek@amd.com
2024-11-26Merge tag 'u-boot-dfu-next-20241126' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dfu into next CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/23573 Android: - bootstd: Implement bootimage v2 support - bootstd: Support non-A/B in bootmeth_android - Migrate VIM3 and VIM3L to use bootmeth_android - bootstd: Additional test for bootimage v2 - bootstd: Optimize load time when reading partitions
2024-11-26bootstd: Add test for Android boot image v2Guillaume La Roque
Rename actual android bootmethod test to specify it's for boot image version 4. Add a unit test for testing the Android bootmethod with boot image version 2. This requires another mmc image (mmc8) to contain the following partitions: - misc: contains the Bootloader Control Block (BCB) - boot_a: contains a fake generic kernel image we can test this with: $ ./test/py/test.py --bd sandbox --build -k test_ut # build the mmc8.img $ ./test/py/test.py --bd sandbox --build -k bootflow_android Reviewed-by: Mattijs Korpershoek <[email protected]> Signed-off-by: Guillaume La Roque <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mattijs Korpershoek <[email protected]>
2024-11-25board: phytec: phycore-imx8mm: Add EEPROM detection initialisationYunus Bas
Add EEPROM detection initialisation for phyCORE-i.MX8MM. Signed-off-by: Yunus Bas <[email protected]>
2024-11-25board: phytec: imx93: Add phyCORE-i.MX 93 support for all SOM variantsChristoph Stoidner
The phyCORE-i.MX 93 is available in various variants (e.g. different ram sizes, eMMC HS400 yes/no). Enable hardware introspection for the imx93-phyboard-segin_defconfig, so that during startup the SOM module variant can be detected, and the hardware can be configured accordingly. The resulting SPL and u-boot binary shall able to boot each phyCORE-i.MX 93 module variant on each carrier board. Finally rename imx93-phyboard-segin_defconfig to imx93-phycore_defconfig, to highlight its SOM scope. Signed-off-by: Christoph Stoidner <[email protected]> Reviewed-by: Wadim Egorov <[email protected]> Reviewed-by: Yannic Moog <[email protected]>
2024-11-25board: phytec: imx93: Add eeprom-based hardware introspectionChristoph Stoidner
The phyCORE-i.MX 93 is available in various variants. Relevant variant options for the spl/u-boot are: - with or without HS400 support for the eMMC - with 1GB ram chip, or 2GB ram chip The phyCORE's eeprom contains all information about the existing variant options. Add evaluation of the eeprom data to the spl/u-boot to enable/disable HS400 and to select the appropriate ram configuration at startup. Signed-off-by: Christoph Stoidner <[email protected]> Reviewed-by: Wadim Egorov <[email protected]> Reviewed-by: Yannic Moog <[email protected]> Tested-by: Primoz Fiser <[email protected]>
2024-11-25siemens: imx8-capricorn.dtsi: add wdt deviceHeiko Schocher
add wdt device Signed-off-by: Heiko Schocher <[email protected]>
2024-11-25siemens: imx8qxp-capricorn-u-boot.dtsi: fix bootHeiko Schocher
current generated flash.bin image does not longer boot on cxg3 board. Rename bootph-pre-ram to bootph-all so flash.bin boots again! Add u-boot specific change (add bootph-all property) in A35_0 node to imx8qxp-capricorn-u-boot.dtsi Signed-off-by: Heiko Schocher <[email protected]> Reviewed-by: Alexander Sverdlin <[email protected]>
2024-11-25siemens: capricorn: move to cxg3 reference project with deneb boardEnrico Leto
We have many HW with capricorn i.MX8X boards. The difference in u-boot is at all by the display of the LEDs. * put upstream a reference project & board for DT and defconfig * use the capricorn prefix outside the board/siemens/capricorn folder Signed-off-by: Enrico Leto <[email protected]> Signed-off-by: Heiko Schocher <[email protected]>
2024-11-25imx8qxp: Fix build when using SPLHeiko Schocher
imx8qxp based boards which use SPL drop error when calling make all: """ Writing image to './flash.bin' Node '/binman/imx-boot/spl': GetData: size 0x0 Node '/binman/imx-boot': GetPaddedDataForEntry: size 0x0 Node '/binman/imx-boot': GetData: 1 entries, total size 0x0 Node '/binman/imx-boot': GetPaddedDataForEntry: size 0x0 Wrote 0x0 bytes Image 'imx-boot' is missing external blobs and is non-functional: spl /binman/imx-boot/spl (spl.bin): Missing blob Some images are invalid """ Guard creation of flash.bin with CONFIG_XPL_BUILD option. Signed-off-by: Heiko Schocher <[email protected]> Fixes: c9713c155127 ("imx8-u-boot: Fix SPL guard option")
2024-11-25Merge tag 'v2025.01-rc3' into nextTom Rini
Prepare v2025.01-rc3
2024-11-25ast2600: spl: Use readl for reading mmioJoel Stanley
u-boot was crashing in qemu as the modeled hardware enforced overly strict memory reads. While this code will work on existing hardware, fix to avoid future issues. Fixes: 12770d0df0e8 ("ast2600: spl: Add boot mode detection") Link: https://gitlab.com/qemu-project/qemu/-/issues/2636 Signed-off-by: Joel Stanley <[email protected]>
2024-11-24Merge patch series "Fix device removal order for Apple dart iommu"Tom Rini
Janne Grunau <[email protected]> says: Starting with v2024.10 dev_iommu_dma_unmap calls during device removal trigger a NULL pointer dereference in the Apple dart iommu driver. The iommu device is removed before its user. The sparsely used DM_FLAG_VITAL flag is intended to describe this dependency. Add it to the driver. Adding this flag is unfortunately not enough since the boot routines except the arm one simply remove all drivers. Add and use a new function which calls dm_remove_devioce_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL); dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); to ensure this order dependency is head consistently. Link: https://lore.kernel.org/r/[email protected]
2024-11-24dm: Add dm_remove_devices_active() for ordered device removalJanne Grunau
This replaces dm_remove_devices_flags() calls in all boot implementations to ensure non vital devices are consistently removed first. All boot implementation except arch/arm/lib/bootm.c currently just call dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL). This can result in crashes when dependencies between devices exists. The driver model's design document describes DM_FLAG_VITAL as "indicates that the device is 'vital' to the operation of other devices". Device removal at boot should follow this. Instead of adding dm_remove_devices_flags() with (DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL) everywhere add dm_remove_devices_active() which does this. Fixes a NULL pointer deref in the apple dart IOMMU driver during EFI boot. The xhci-pci (driver which depends on the IOMMU to work) removes its mapping on removal. This explodes when the IOMMU device was removed first. dm_remove_devices_flags() is kept since it is used for testing of device_remove() calls in dm. Signed-off-by: Janne Grunau <[email protected]>
2024-11-23arm64: dts: imx8mn: Include 32kHz oscillator clock in SPL DTsMarek Vasut
Since 50cdd3f74af3 ("clk: imx: clk-imx8mn Fix nand and spi clock parent"), drivers/clk/imx/clk-imx8mn.c clk_get_by_name(dev, "osc_24m", &osc_24m_clk) fails with error -22 EINVAL in SPL. This is because clk_get_by_name() in the end calls fdtdec_parse_phandle_with_args(), which iterates over all phandles in clock-controller@30380000 { clocks = <&osc_32k>, <&osc_24m>, ... } node 'clocks' property in an attempt to find the "osc_24m" clock, but fails to resolve the &osc_32k phandle and returns with -EINVAL. Include the osc_32k clock in SPL DTs as a low risk fix for v2025.01 release. This way, fdtdec_parse_phandle_with_args() can resolve both the osc_32k and following osc_24m phandle and successfully look up the osc_24m clock. Fixes: 50cdd3f74af3 ("clk: imx: clk-imx8mn Fix nand and spi clock parent") Signed-off-by: Marek Vasut <[email protected]> Tested-by: Adam Ford <[email protected]> #imx8mn-beacon
2024-11-20Merge branch 'qcom-main' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-snapdragon CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/23474 - UFS support is enabled for SC7280 and SM8150 platforms. - Qualcomm dt-bindings headers are all dropped in favour of dts/upstream. - The SMMU driver now correctly handles stream ID 0 and is disabled in EL2. - Initial support for capsule updates (using the new dynamic UUIDs) is added for the RB3 Gen 2 board alongside a new SCSI backend for DFU. - CONFIG_PINCONF is enabled in qcom_defconfig. - The vqmmc supply is now enabled for sdcard support on boards that need it. - A quirk is added for reading GPIOs on the PM8550 PMIC
2024-11-20mach-snapdragon: implement capsule update supportCaleb Connolly
Qualcomm boards flash U-Boot a variety of partitions, implement support for determining which slot U-Boot is running from, finding the correct partition for that slot and configuring the appropriate DFU string. Initially, we only support the RB3 Gen 2 where U-Boot is flashed to the UEFI partition, and ignore handling of slots. In the future we will additionally support booting U-Boot from other partitions (e.g. boot) and correct handling for A/B. Reviewed-by: Neil Armstrong <[email protected]> Acked-by: Ilias Apalodimas <[email protected]> Signed-off-by: Caleb Connolly <[email protected]>
2024-11-20mach-snapdragon: configure loggingCaleb Connolly
Set LOG_CATEGORY and pr_fmt. Also fix the time.h include. Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Caleb Connolly <[email protected]>
2024-11-20ARM: mach-snapdragon: configure a larger default SYS_MALLOC_LEN for fastbootNeil Armstrong
Fastboot is very hungry when it flashes larges chunks, and 8MiB is way too small, allocate a much bigger size like other platforms using Fastboot. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Caleb Connolly <[email protected]> # rb1 Reviewed-by: Caleb Connolly <[email protected]>
2024-11-19Merge tag 'xilinx-for-v2025.01-rc3-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze AMD/Xilinx changes for v2025.01-rc3: - microblaze: - Disable JFFS2 - fpga: - pass compatible flag to fpga_load() - zynqmp: - SOM RTC fix - SC(system controller) PMW polarity fix - Fix ram_top calculation with introducing XILINX_MINI - Fix RPU release command - versal: - Enable capsule update - Enable soft reset and Micron octal flashes - xilinx: - Align Kconfig regarding SPI_STACKED_PARALLEL - bootcount: - Add new zynqmp driver
2024-11-17armv8: cpu: Implement allow_unaligned()Sam Protsenko
Usually ARMv8 platforms allow unaligned access for Normal memory. But some chips might not allow it by default, having SCTLR.A bit set to 1 before U-Boot execution. One such example is Exynos850 SoC. As allow_unaligned() is not implemented for ARMv8 at the moment, its __weak implementation is used, which does nothing. That might lead to unaligned access abort, for example when running EFI selftest. Fix that by implementing allow_unaligned() for ARMv8. The issue was found when running EFI selftest on E850-96 board (Exynos850 based): => bootefi selftest $fdtcontroladdr ... Executing 'HII database protocols' "Synchronous Abort" handler, esr 0x96000021, far 0xbaac0991 ... resetting ... Unaligned abort happens in u16_strnlen(), which is called from efi_hii_sibt_string_ucs2_block_next(): u16_strlen(blk->string_text) where 'blk' type is struct efi_hii_sibt_string_ucs2_block. Because this struct is packed, doing "->string_text" makes 'blk' address incremented by 1 byte, which makes it unaligned. Although allow_unaligned() was called in efi_init_early() before EFI selftest execution, it wasn't implemented for ARMv8 CPUs, so data abort happened. Signed-off-by: Sam Protsenko <[email protected]>
2024-11-17armv8: Fix get_sctlr() return typeSam Protsenko
SCTLR_EL2 is a 64-bit register [1]. Return its value as long (64 bit) instead of int (32 bit) in get_sctlr() to make sure it's not trimmed. [1] https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/SCTLR-EL2--System-Control-Register--EL2-?lang=en Fixes: 0ae7653128c8 ("arm64: core support") Suggested-by: Heinrich Schuchardt <[email protected]> Signed-off-by: Sam Protsenko <[email protected]> Reviewed-by: Ilias Apalodimas <[email protected]>
2024-11-15imx: Fix critical thermal thresholdFrancesco Dolcini
Fix the critical thermal threshold for i.MX processors, this was changed while moving the code from imx8m/imx9 directories into a shared place. There is no need to keep the critical threshold 5 degrees less than the SoC maximum temperature threshold, what is actually going to happen in practice is that we are going to power-off the board when the SoC is still within its working temperature range. In addition to that this is a change in the actual behavior, that is introducing a regression to users, and it was hidden within a software refactoring. Fixes: d0fe80890ab1 ("imx: Generalize fixup_thermal_trips") Signed-off-by: Francesco Dolcini <[email protected]>
2024-11-15drivers: bootcount: Add ZynqMP specific bootcount supportVasileios Amoiridis
Add native support of the bootcount mechanism in the ZynqMP by utilising internal PMU registers. The Persistent Global Storage Registers of the Platform Management Unit can keep their value during reboot cycles unless there is a POR reset, making them appropriate for the bootcount mechanism. Signed-off-by: Vasileios Amoiridis <[email protected]> Reviewed-by: Heiko Schocher <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2024-11-15arm64: zynqmp: Fix r5 mode for cpu release commandPadmarao Begari
The cpu release command for r5 mode (lockstep/split) argument accepts only string. But the zynqmp tcminit command accepts string or number for r5 mode (lockstep/split or 0/1) argument. To fix the r5 mode argument, the common argument (lockstep/split or 0/1) is used across different u-boot commands. Use the strcmp() instead of strncmp() to make uniform the r5 mode (lockstep/split or 0/1) for the zynqmp tcminit and cpu release command. Signed-off-by: Padmarao Begari <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2024-11-14Merge patch series "Apply SoM overlays on phyCORE-AM6xx SoMs"Tom Rini
Wadim Egorov <[email protected]> says: Our SoMs are available in multiple configurations, managed via device tree overlays. To determine the specific variant in use, we read the EEPROM and apply the appropriate overlays during boot to the device tree used by the OS. Apply overlays for phyCORE-AM62x and phyCORE-AM64x SoMs. Future K3 SoMs will be able to reuse this logic and overlays. Link: https://lore.kernel.org/r/[email protected]
2024-11-14arm: dts: k3-am642-phycore-som-binman: Add SoM overlaysWadim Egorov
Include SoM dt-overlays that handle variants of our SoMs into u-boot's FIT image. Signed-off-by: Wadim Egorov <[email protected]> Reviewed-by: Neha Malcom Francis <[email protected]>
2024-11-14arm: dts: k3-am625-phycore-som-binman: Add SoM overlaysWadim Egorov
Include SoM dt-overlays that handle variants of our SoMs into u-boot's FIT image. Signed-off-by: Wadim Egorov <[email protected]> Reviewed-by: Neha Malcom Francis <[email protected]>
2024-11-14Merge tag 'u-boot-amlogic-next-20241113' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-amlogic into next - khadas-vim3{l}: fix userdata size for android config - drop A1 dtsi and other bindings includes in favor of Upstream ones
2024-11-13arm: dts: meson: remove meson-a1.dtsiAlexey Romanov
For Amlogic A1, we have to use dtsi from dts/upstream folder. The only difference between this two files is the added cpu temperature node definition in upstream version and additional assigned-clock for USB. This patch is tested on a device with A113L SoC (AD401-like) and everything is okay. So, we can remove legacy arch/arm/dts/meson-a1.dtsi file. Signed-off-by: Alexey Romanov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Neil Armstrong <[email protected]>
2024-11-13test: run longjmp() test only on supported architecturesHeinrich Schuchardt
We have only implemented longjmp() on the EFI architectures. Define a symbol CONFIG_HAVE_SETJMP and have it selected by the relevant architectures. Use CONFIG_HAVE_SETJMP to decide if the longjmp test shall be built. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2024-11-12ARM: dts: stm32: Sort DH STM32 DHCOM DTSIMarek Vasut
Sort the DTSI alphabetically. No functional change. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]>
2024-11-12ARM: dts: stm32: Drop duplicate pinmux on DH STM32 DHCOMMarek Vasut
The ethernet0_rmii_pins_a pinmux change has no effect on any DHSOM based hardware. The mco2_pins_a and mco2_sleep_pins_a are both part of stm32mp15-pinctrl.dtsi . Drop both pinmux changes. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]>
2024-11-12ARM: dts: stm32: Drop remnants of upstream DT switch on DH STM32 DHSOMMarek Vasut
Remove unused local DT copies after the OF_UPSTREAM conversion. Fixes: cccb29fc1270 ("ARM: dts: stm32: Switch to using upstream DT on DH STM32 DHSOM") Reported-by: Patrick Delaunay <[email protected]> Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]>
2024-11-12arm64: zynqmp: Fix pwm-fan polaritySaeed Nowshadi
In previous version of pwm driver, the polarity of pwm were implemented in reverse. In recent release, that issue in the driver is fixed, therefore, correctly set the polarity in the device tree. Signed-off-by: Saeed Nowshadi <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/3e8e38b77101335f86bca0f05b3988877bb12993.1729766551.git.michal.simek@amd.com
2024-11-12arm64: zynqmp: Configure SoC RTC on SOMMichal Simek
Use RTC available in HW on Kria SOM without using emulation that's why configure it properly and disable emulated one. Power on reset value of RTC Calibration register without battery backup is not matching with crystal frequency which leads to RTC time drift. That's why write CALIB_WRITE register with crystal frequency (0x7FFF). There is also an option to write zero so that Linux will set default value (0x7FFF) in driver probe but calibration 0 is not permited by DT schema. Co-developed-by: Srinivas Goud <[email protected]> Signed-off-by: Srinivas Goud <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/9b684faeec85381b9b8fe796aaebc2ee79f17b8e.1729663761.git.michal.simek@amd.com
2024-11-11Merge tag 'u-boot-rockchip-20241111' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/23280 - Add board: rk3328: FriendlyElec NanoPi R2S Plus rk3568: Qnap TS433 rk3588: Cool Pi CM5 GenBook - Move rk3399_force_power_on_reset to TPL for puma board;
2024-11-11rockchip: rk3399: move sysreset-gpio logic to TPLQuentin Schulz
If TPL_GPIO and TPL_PINCTRL_ROCKCHIP are enabled and a sysreset-gpio is provided in the TPL Device Tree, this will trigger a system reset similar to what's currently been done in SPL whenever the RK3399 "warm" boots. Because there's currently only one user of sysreset-gpio logic, and TPL is enabled on that board, so let's migrate the logic and that board to do it in TPL. There are three reasons for moving this earlier: - faster boot time as we don't need to reach SPL to be able to reset the system on a condition we know is already met in TPL, - have less code to be impacted by the issue this system reset works around (that is, "unclean" SoC registers after a reboot), - less confusion around the reason for restarting. Indeed when done from SPL, the following log can be observed: """ U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45) Channel 0: DDR3, 666MHz BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB Channel 1: DDR3, 666MHz BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB 256B stride Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45 +0100) Trying to boot from MMC2 U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45) """ possibly hinting at an issue within the SPL when loading the fitImage from MMC2 instead of the normal course of events (a system reset). Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Paul Kocialkowski <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2024-11-11rockchip: tpl: allow to call board/SoC-specific code before DRAM initQuentin Schulz
This defines a weak tpl_board_init function that can be used for running board/SoC-specific code before the DRAM init happens, similarly to spl_board_init() for SPL. Reviewed-by: Paul Kocialkowski <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2024-11-11rockchip: rk3399: merge CRU check within rk3399_force_power_on_resetQuentin Schulz
To prepare to support forcing power on reset from TPL which would have the exact same logic, just in an earlier stage, let's merge the CRU check that triggers the power on reset with the rest of the logic. Reviewed-by: Paul Kocialkowski <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2024-11-11board: rockchip: Add FriendlyElec NanoPi R2S PlusJonas Karlman
The FriendlyElec NanoPi R2S Plus is a single-board computer based on Rockchip RK3328 SoC. It features e.g. 1 GB DDR4 RAM, 32 GB eMMC, SD-card, 2x GbE LAN, optional M.2 SDIO Wi-Fi and 2x USB 2.0 host. Features tested on a NanoPi R2S Plus 2309: - SD-card boot - eMMC boot - Ethernet - USB gadget - USB host Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2024-11-11board: rockchip: Add support for rk3588 GenBookAndy Yan
Add support for Cool Pi GenBook, it works as a carrier board connect with CM5 SOM. Specification: - Rockchip RK3588 - LPDDR5X 8/32 GB - eMMC 64 GB - HDMI Type A out x 1 - USB 3.0 Host x 1 - USB-C 3.0 with DisplayPort AltMode - PCIE M.2 E Key for RTL8852BE Wireless connection - PCIE M.2 M Key for NVME connection - eDP panel with 1920x1080 Tested by Armbian boot on USB disk. Change-Id: I4d9b8572dc7c400077dde666633f3fea1b47dd03 Signed-off-by: Andy Yan <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2024-11-11board: rockchip: add support for Qnap TS433 devicesHeiko Stuebner
The Qnap TS433 is a 4-bay NAS based around the RK3568. Two SATA bays are connected to the RK3568's own SATA controllers while the other two are connected to a JMicron SATA controller living on the PCIe bus. It provides one 2.5Gb and one 1Gb ethernet port as well as 3 usb ports. Signed-off-by: Heiko Stuebner <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2024-11-10board: hoperun: Switch to use complete DTS files from upstream DTSLad Prabhakar
For upstream Linux kernel we use below DTBs for HiHope boards: - r8a774a1-hihope-rzg2m-ex.dtb - r8a774e1-hihope-rzg2h-ex.dtb - r8a774b1-hihope-rzg2n-ex.dtb Update the CONFIG_OF_LIST to match the above. Now that we have switched upstream DTS, drop deleting the nodes and also rename the r8a774*-u-boot.dtsi files to r8a774*-ex-u-boot.dtsi to match the OF_LIST files so that the `bootph-all` property gets applied to required nodes in upstream DTS. Signed-off-by: Lad Prabhakar <[email protected]> Signed-off-by: Chris Paterson <[email protected]>
2024-11-10arm: renesas: Fix RZ/G2L GICR base addressPaul Barker
When support for the Renesas RZ/G2L SoC was added, the GICR base address for CPU1 was accidentally used. We should instead supply the GICR base address for CPU0 so that interrupts are correctly configured for the CPU core that U-Boot is actually using. Fixes: 387d4275ab0e ("arm: rmobile: Add basic RZ/G2L family support") Signed-off-by: Paul Barker <[email protected]>
2024-11-10ARM: dts: Drop unused RZ/G2L devicetreesPaul Barker
We are now using the dts/upstream subtree for the RZ/G2L SoC family so we can drop unused devicetree files from arch/arm/dts. Signed-off-by: Paul Barker <[email protected]> Reviewed-by: Marek Vasut <[email protected]>
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