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So far we used inline assembly to inject the actual instruction that
triggers the semihosting service. While this sounds elegant, as it's
really only about a few instructions, it has some serious downsides:
- We need some barriers in place to force the compiler to issue writes
to a data structure before issuing the trap instruction.
- We need to convince the compiler to actually fill the structures that
we use pointers to.
- We need a memory clobber to avoid the compiler caching the data in
those structures, when semihosting writes data back.
- We need register arguments to make sure the function ID and the
pointer land in the right registers.
This is all doable, but fragile and somewhat cumbersome. Since we now
have a separate function in an extra file anyway, we can do away with
all the magic and just write that in an actual assembler.
This is much more readable and robust.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
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So far we used inline assembly to inject the actual instruction that
triggers the semihosting service. While this sounds elegant, as it's
really only about one instruction, it has some serious downsides:
- We need some barriers in place to force the compiler to issue writes
to a data structure before issuing the trap instruction.
- We need to convince the compiler to actually fill the structures that
we use pointers to.
- We need a memory clobber to avoid the compiler caching the data in
those structures, when semihosting writes data back.
- We need register arguments to make sure the function ID and the
pointer land in the right registers.
This is all doable, but fragile and somewhat cumbersome. Since we now
have a separate function in an extra file anyway, we can do away with
all the magic and just write that in an actual assembly file.
This is much more readable and robust.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
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AM62A7-SK board has 4GB LPDDR4 Micron MT53E2G32D4DE-046 AUT:B part
but only 2GB was enabled early.
Enable full 4GB memory by updating the latter 2GB memory region
which gets mapped to 0x0880000000 i.e. DDR16SS0_SDRAM as referred in
Table 2-1. AM62A Common SoC Memory of AM62Ax TRM [1].
[1] : https://www.ti.com/lit/zip/spruj16
Logs: https://gist.github.com/devarsht/e85b6af89c01ddadb3a62f3e5f196af8
Signed-off-by: Devarsh Thakkar <[email protected]>
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Synchronize devicetree sources with Linux v6.2.
- Use GIC interrupt definitions
- Add reg properties in USB-glue and SoC-glue node
- Fix node names to follow the generic names list in DT specification
- Add L2 cache and AHCI nodes
- Update nand and pcie nodes
- And some trivial fixes
Signed-off-by: Kunihiko Hayashi <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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UniPhier DT applies its own USB node for U-Boot due to the USB driver
constrains. After solving this issue, u-boot allows the original USB node.
After switching USB node, synchronization of USB node with Linux becomes
possible.
Signed-off-by: Kunihiko Hayashi <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Commit fe7d654d04 ("mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to
Kconfig") converted CONFIG_SYS_{BRx/ORx}_PRELIM to Kconfig by
implementing a fine-grained selection of every bit in Kconfig.
But commit c7fad78ec0 ("Convert CONFIG_SYS_BR0_PRELIM et al to
Kconfig") reworked it so that you now just have to provide the raw
value of each register in Kconfig. However, all fine-grained
Kconfig items remained allthough they are not used anymore.
Remove them all.
Fixes: c7fad78ec0 ("Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig")
Signed-off-by: Christophe Leroy <[email protected]>
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As the lastest spear directories are removed, delete the associated entry
in Makefile.
Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support")
Signed-off-by: Patrick Delaunay <[email protected]>
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count_required_pts()'s complexity is high if mappings are not using the
largest possible block size (due to some other requirement such as tracking
dirty pages, for example).
Let's switch to a method that follows the pattern established with
the add_map() helper, and make it almost instantaneous instead of
taking a large amount of time if 2MB mappings are in use instead of
1GB.
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Pierre-Clément Tosi <[email protected]>
[ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the
upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <[email protected]>
Cc: Tom Rini <[email protected]>
Link: https://android.googlesource.com/platform/external/u-boot/+/5d756d147e31a1cdaaa261a50e526404ca5968f5
Link: https://android.googlesource.com/platform/external/u-boot/+/6be9330601d81545c7c941e3609f35bf68a09059
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In the add_map() function, for each level it populates, it iterates from
the root of the PT tree, making it ineficient if a mapping needs to occur
past level 1.
Instead, replace it with a recursive (and much simpler) algorithm
that keeps the complexity as low as possible. With this, mapping
512GB at level 2 goes from several seconds down to not measurable
on an A55 machine.
We keep the block mappings at level 1 for now though.
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Pierre-Clément Tosi <[email protected]>
[ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the
upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <[email protected]>
Cc: Tom Rini <[email protected]>
Link: https://android.googlesource.com/platform/external/u-boot/+/96ad729cf4cab53bdff8222bb3eb256f38b5c3a6
Link: https://android.googlesource.com/platform/external/u-boot/+/6be9330601d81545c7c941e3609f35bf68a09059
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Memory used to hold the page tables is allocated from the top of RAM
with no prior initialization and could therefore hold invalid data. As
invalidate_dcache_all() will be called before the MMU has been
initialized and as that function relies indirectly on the page tables
when using CMO_BY_VA_ONLY, these must be in a valid state from their
allocation.
Signed-off-by: Pierre-Clément Tosi <[email protected]>
[ Paul: pick from the Android tree. Fix checkpatch warnings, and rebased
to the upstream. ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <[email protected]>
Cc: Tom Rini <[email protected]>
Link: https://android.googlesource.com/platform/external/u-boot/+/e3ceef4230b772186c6853cace4a676a407e6ab7
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Exposing set/way cache maintenance to a virtual machine is unsafe, not
least because the instructions are not permission-checked but also
because they are not broadcast between CPUs. Consequently, KVM traps and
emulates such maintenance in the host kernel using by-VA operations and
looping over the stage-2 page-tables. However, when running under
protected KVM, these instructions are not able to be emulated and will
instead result in an exception being delivered to the guest.
Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select
this option and perform by-VA cache maintenance instead of using the
set/way instructions.
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Pierre-Clément Tosi <[email protected]>
[ Paul: pick from the Android tree. Fixup Pierre's commit. And fix some
checkpatch warnings. Rebased to upstream. ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <[email protected]>
Cc: Tom Rini <[email protected]>
Link: https://android.googlesource.com/platform/external/u-boot/+/db5507f47f4f57f766d52f753ff2cc761afc213b
Link: https://android.googlesource.com/platform/external/u-boot/+/2baf54e743380a1e4a6bc2dbdde020a2e783ff67
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This is used by ls1021atwr_sdcard_ifc_SECURE_BOOT with split config, but
is not needed anymore, since Ethernet migration is complete. Drop it.
Signed-off-by: Simon Glass <[email protected]>
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Avoid using CONFIG_SANDBOX_VPL since we have a generic option which works
just as well.
Signed-off-by: Simon Glass <[email protected]>
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At present we enable the sandbox RTC driver for all builds. Add a separate
Kconfig option to control this, so that it can be disabled in TPL, where
it is not needed.
Signed-off-by: Simon Glass <[email protected]>
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Allow this to get larger to accommodate more test code with LTO disabled.
Signed-off-by: Simon Glass <[email protected]>
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We don't need to provide an empty arch_misc_init function here, we can
just not enable the hook.
Cc: Stefan Bosch <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Minkyu Kang <[email protected]>
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If this hooks is needed later, it should be added and populated for
real.
Cc: Stefan Roese <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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In this platform, arch_misc_init doesn't perform any real function. The
call to get_soc_type_rev has no lasting side effects.
Cc: Chris Packham <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Chris Packham <[email protected]>
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We don't need an empty function, we can just not enable the hook we
don't use.
Cc: Peng Fan <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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On the lion and evb-px5 platforms, we need this function, so select it.
Cc: Andy Yan <[email protected]>
Cc: Quentin Schulz <[email protected]>
Cc: Klaus Goger <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
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The function arch_early_init_r only does anything on these platforms if
we have FPGA (or SPL and SPL_FPGA) enabled, so move the logic to select
based on that.
Cc: Michal Simek <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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We need to be calling arch_early_init_r() on 64bit mvebu platforms, so
move this to a select.
Cc: Stefan Roese <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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In SPL are active memory maps set by the BootROM. Define them in cpu.h file
to the correct values. Some peripherals are not mapped at all.
Signed-off-by: Pali Rohár <[email protected]>
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Proper U-Boot moves SPI0 CS0 Flash mapping from 0xD4000000 to 0xF4000000
and change its size from 64 MB to 8 MB. Definitions are already in
MBUS_SPI_BASE/MBUS_SPI_SIZE macros. So define these macros also for SPL
build, use them in env_sf_get_env_addr() function and move this function
from spl.c to cpu.c to be available in Proper U-Boot too.
Signed-off-by: Pali Rohár <[email protected]>
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Signed-off-by: Pali Rohár <[email protected]>
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Signed-off-by: Pali Rohár <[email protected]>
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MVEBU_SPL_BOOT_DEVICE_SPI is for NOR flash. Either serial or parallel. Not
for general serial/SPI devices. The correct name should be BOOT_DEVICE_NOR
but name SPI is already used in mkimage config format which we do not want
to change for compatibility reasons.
MVEBU_SPL_BOOT_DEVICE_MMC is for MMC and SD compatible devices. Not for
SDIO devices. In most cases used for eMMC or SD card.
Signed-off-by: Pali Rohár <[email protected]>
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Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_PEX which instruct
make to generate kwbimage with PEX header. This image is used for booting
from PCI Express device which is in the Root Complex mode.
Support is very simple, SPL after finishes DDR training returns back to the
BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then start
executing U-Boot proper.
Signed-off-by: Pali Rohár <[email protected]>
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Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct
make to generate kwbimage with NAND header. This image is used for booting
from NAND flash (either SPI or parallel).
Support is very simple, SPL after finishes DDR training returns back to the
BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and
executes U-Boot proper.
To generate correct kwbimage NAND header, it is required to set following
Kconfig options:
CONFIG_SYS_NAND_PAGE_SIZE
CONFIG_SYS_NAND_BLOCK_SIZE
CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION
They are used only by make / mkimage when generating final kwbimage.
CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION is a new mvebu specific Kconfig
option which is set into kwbimage NAND_BADBLK_LOCATION header field.
Signed-off-by: Pali Rohár <[email protected]>
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Marvell BootROM loads MMC image from sector 0 (HW boot or data partition)
and SD image from sector 1.
So for SD card booting it is needed to not use constant CONFIG MMC options
and instead of them it is needed to define functions spl_mmc_boot_mode()
spl_mmc_get_uboot_raw_sector() which determinate offsets at SPL runtime
based on MMC or SD card.
Calculation of SD card sector expects following values:
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <[email protected]>
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When eMMC boot is selected then BootROM loads kwbimage header (U-Boot SPL)
from the selected eMMC boot partition. So for eMMC boot ensure that U-Boot
SPL loads U-Boot proper (from kwbimage) also from the same selected eMMC
boot partition.
Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <[email protected]>
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BOOT_DEVICE_MMC2 and BOOT_DEVICE_MMC2_2 are representing mmc dev 1 but all
Armada SoCs have only one mmc controller. So remove references to
non-existent second mmc controller.
Fixes: f830703f4284 ("arm: mvebu: Check that kwbimage blockid matches boot mode")
Signed-off-by: Pali Rohár <[email protected]>
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Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.
To process SATA kwbimage and load U-Boot proper from it in the same way as
Marvell BootROM, it is needed to interpret srcaddr as relative offset to
the main header. This change fixes booting of U-Boot proper from SPL code
in SATA image.
Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <[email protected]>
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Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).
To process SDIO kwbimage and load U-Boot proper from it in the same way as
Marvell BootROM, it is needed to interpret srcaddr in bytes. This change
fixes booting of U-Boot proper from SPL code stored in SDIO image.
Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <[email protected]>
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Currently there is only one test and it only works on TPM v2. Update it
to work on v1.2 as well, using a new function to pick up the required
TPM.
Update sandbox to include both a v1.2 and v2 TPM so that this works.
Split out the existing test into two pieces, one for init and one for
the v2-only report_state feature.
Acked-by: Ilias Apalodimas <[email protected]
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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Prepare v2023.04-rc3
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This function allows updating bootloader from u-boot
on production devices without need in host PC.
Be aware! It works only with re-crypt BCT.
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 T20
Signed-off-by: Ramin Khonsari <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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This function allows updating bootloader from u-boot
on production devices without need in host PC.
Be aware! It works only with re-crypted BCT.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <[email protected]> # LG P895 T30
Signed-off-by: Ramin Khonsari <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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Add support for encryption, decryption and signinig with
non-zero key saving backward compatibility.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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Move crypto module from T20 only into common Tegra dir.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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Configure PMIC voltages for early stages using updated
early i2c write.
Tested-by: Thierry Reding <[email protected]> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom <[email protected]>
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This implementation allows pwr i2c writing on early SPL
stages when DM is not yet setup.
Such writing is needed to configure main voltages of PMIC
on early SPL for bootloader to boot properly.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF T30
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <[email protected]> # LG P895 T30
Tested-by: Thierry Reding <[email protected]> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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Late init function allows passing values like identifiers and
perform device specific configurations of pre-boot stage.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <[email protected]> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.
Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.
This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/[email protected]/
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF T30
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <[email protected]> # ASUS TF201 T30
Tested-by: Thierry Reding <[email protected]> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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On T30 unlike T20 dsi panels are wider used on devices
and PLLD is used as DISP1 parent more often, so lets
enable it as well for this cases.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF700T T30
Tested-by: Svyatoslav Ryhel <[email protected]> # HTC One X T30
Tested-by: Thierry Reding <[email protected]> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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Get periph clock id and its parent from device tree.
This works by looking up the peripheral's 'clocks' node and
reading out the second and fourth cells, which are the
peripheral and PLL clock numbers.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF T30
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <[email protected]> # HTC One X
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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This function allows to convert a device tree clock ID to PLL ID.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF T30
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <[email protected]> # HTC One X
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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According to mainline clock tables and TRM HOST1X
parent is PLLC, while DISP1 usually uses PLLP as
parent clock.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF T30
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <[email protected]> # LG P895 T30
Tested-by: Thierry Reding <[email protected]> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
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This mappings were missing for some reason.
Tested-by: Svyatoslav Ryhel <[email protected]> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom <[email protected]>
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