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APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated
4/27/11) states that rev D processors may wake up with the wrong feature
set. This patch implements the APM-proposed workaround.
To enable this patch for your board, add the appropriate define for your
CPU to your board header file. See kilauea.h for more information. The
following variants are supported:
#define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
Please note that if you select the wrong define, your board will not
boot, and JTAG will be required to recover.
Tested on custom boards using:
CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <[email protected]>
CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <[email protected]>
Signed-off-by: Steve Falco <[email protected]>
Acked-by: Dirk Eibach <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch allow to override CONFIG_SYS_TCLK from board configuration
files. This is needed for the Network Space v2 which use a non standard
core clock frequency (166MHz instead of 200MHz for a 6281 SoC).
As a possible enhancement for 6281 and 6282 devices, TCLK could be
dynamically detected by checking the Sample at Reset register bit 21.
Additionally this patch fix a typo.
Signed-off-by: Simon Guinot <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
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Drop warnings in get_cpu_rev and changes the return value
(a u32 instead of char * is returned) of the function
to be coherent with other processors.
Signed-off-by: Stefano Babic <[email protected]>
CC: Detlev Zundel <[email protected]>
CC: Fabio Estevam <[email protected]>
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Drop warning caused by missing prototype for
mxc_hw_watchdog_reset().
Signed-off-by: Stefano Babic <[email protected]>
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Current timer routines (arch/mips/lib/timer.c) are implemented assuming
that MIPS32 coprocessor (CP0) resources, Counter and Compare registers
in this case, are available. But this doesn't always work.
We need to make sure that all MIPS-based systems don't necessarily use
CP0 counter/compare registers as time keeping resources. And some MIPS
variant processors might come with different hardware specs with genuine
MIPS32 CP0 registers.
With this change, each $(CPU)/ directory can have its own timer code.
Signed-off-by: Shinya Kuribayashi <[email protected]>
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All architectures but MIPS are using --gc-sections on final linking.
This patch introduces that feature for MIPS to reduce the memory and
flash footprint.
Signed-off-by: Daniel Schwierzeck <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Thomas Lange <[email protected]>
Cc: Vlad Lungu <[email protected]>
Signed-off-by: Shinya Kuribayashi <[email protected]>
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Fix style issues and alignments globally. No logical changes.
- Replace C comments with AS line comments where possible
- Use ifndef where possible, rather than if !defined for simplicity
- An instruction executed in a delay slot is now indicated by a leading
space, not by C comment
Signed-off-by: Shinya Kuribayashi <[email protected]>
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As requested in commit e1390801a3c1a2b6d12fa90be368efc19f5b9bfd ([MIPS]
Request for the 'mips_cache_lock()' removal), such feature is no longer
needed for current MIPS implementation of U-Boot, and no one in the tree
uses it for years.
Signed-off-by: Shinya Kuribayashi <[email protected]>
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Currently, some linker scripts are found by common code in config.mk.
Some are found using CONFIG_SYS_LDSCRIPT, but the code for that is
sometimes in arch config.mk and sometimes in board config.mk. Some
are found using an arch-specific rule for looking in CPUDIR, etc.
Further, the powerpc config.mk rule relied on CONFIG_NAND_SPL
when it really wanted CONFIG_NAND_U_BOOT -- which covered up the fact
that not all NAND_U_BOOT builds actually wanted CPUDIR/u-boot-nand.lds.
Replace all of this -- except for a handful of boards that are actually
selecting a linker script in a unique way -- with centralized ldscript
finding.
If board code specifies LDSCRIPT, that will be used.
Otherwise, if CONFIG_SYS_LDSCRIPT is specified, that will be used.
If neither of these are specified, then the central config.mk will
check for the existence of the following, in order:
$(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT)
$(TOPDIR)/$(CPUDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT)
$(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
$(TOPDIR)/$(CPUDIR)/u-boot.lds
Some boards (sc3, cm5200, munices) provided their own u-boot.lds that
were dead code, because they were overridden by a CPUDIR u-boot.lds under
the old powerpc rules. These boards' own u-boot.lds have bitrotted and
no longer work -- these lds files have been removed.
Signed-off-by: Scott Wood <[email protected]>
Tested-by: Graeme Russ <[email protected]>
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- serial console on UART1
- Ethernet RMII over UCC4
- PHY SMSC LAN8700
- 64MB Flash
- 128 MB DDR2 RAM
- I2C
- bootcount
This board is similiar to the kmeter1 (8360) board,
so common config options are extracted into the
include/configs/km83xx-common.h file.
Signed-off-by: Heiko Schocher <[email protected]>
Acked-by: Kim Phillips <[email protected]>
cc: Kim Phillips <[email protected]>
cc: Holger Brunck <[email protected]>
cc: Valentin Longchamp <[email protected]>
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Signed-off-by: Kyle Moffett <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Mingkai Hu <[email protected]>
Singed-off-by: Jerry Huang <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
Cc: Mike Frysinger <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts. All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.
Signed-off-by: Kumar Gala <[email protected]>
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Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1
are swapped.
Erratum SERDES-A001 says that if bank two is kept disabled and after bank
three is enabled, then the PLL for bank three won't lock properly. The
work-around is to enable and then disable bank two after bank three is
enabled.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Part of the SERDES9 erratum work-around is to set some bits in the SerDes
TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The
current code does this only for XAUI, so extend it to the other protocols.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The work-around for P4080 erratum SERDES-8 requires all lanes of banks two
and three to be disabled (powered down) in the RCW. Display a warning
message if this is not the case.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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SerDes PLL bandwidth default setting is incorrect when no lanes are
configured as PCI Express.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Use the 'video-mode' environment variable (for Freescale chips that have a
DIU display controller) to designate the full video configuration. Previously,
the DIU driver used the 'monitor' variable, and it was used only to determine
the output video port.
The old definition of the "monitor" environment variable only determines
which video port to use for output. This variable was set to a number (0,
1, or sometimes 2) to specify a DVI, LVDS, or Dual-LVDS port. The
resolution was hard-coded into board-specific code. The Linux command-line
arguments needed to be hard-coded to the proper video definition string.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Anatolij Gustschin <[email protected]>
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A lot of boards set FT_FSL_PCI_SETUP directly in their board code
and don't check to see if CONFIG_PCI is actually defined. This
will cause the board compilation to fail if CONFIG_PCI is not
defined. The p1022ds board is one such example.
Instead of fixing every board this patch wraps FT_FSL_PCI_SETUP
around CONFIG_PCI so we can remove CONFIG_PCI and boards will
still build properly.
Signed-off-by: Matthew McClintock <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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versioned SEC properties changed names during development, so
for now search and update LIODNs for both "secX.Y" and
"sec-vX.Y" based properties.
Signed-off-by: Kim Phillips <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The workaround for ESDHC111 should also be applied on
P2040/P3041/P5010/P5020 SoCs.
Signed-off-by: Lei Xu <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we
need to enable for them to function.
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The P3041DS & P5020DS boards are almost identical (except for the
processor in them). Additionally they are based on the P4080DS board
design so we use the some board code for all 3 boards.
Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have
meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock
configuration.
Additionally, the P3041DS/P5020DS support NAND.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Emil Medve <[email protected]>
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Rework and add some new APIs to the fsl_corenet_serdes code for use by
erratum and drivers.
* Rename serdes_get_bank() to serdes_get_bank_by_lane()
* Add serdes_get_first_lane returns which SERDES lane is used by device
Signed-off-by: Emil Medve <[email protected]>
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Fix fdt bportal to pass the bman revision number to kernel via device tree.
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Second USB controller only works for SPI and SD boot because of pin muxing
Signed-off-by: Ramneek Mehresh <[email protected]>
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Signed-off-by: Dipen Dudhat <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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To make sure that machine change operation work successfully, change
timing parameters first before changing machine for chip select on IFC.
Signed-off-by: Dipen Dudhat <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Timur Tabi <[email protected]>
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If FB address is defined specific address then don't grab memory for LCD
Signed-off-by: Minkyu Kang <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Kim Phillips <[email protected]>
Cc: Andy Fleming <[email protected]>
Cc: Kumar Gala <[email protected]>
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Move the header file and definitions of ftsmc020
static memory control unit from a320 SoC folder to
"drivers/mtd" folder.
This change will let other SoC which also use ftsmc020
could share the same header file.
Signed-off-by: Macpaul Lin <[email protected]>
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Move the header file "ftsdmc020.h" (SDRAM Controller)
to "include/faraday" folder.
This change will let other SoC which also use ftsdmc020
could share the same header file.
Signed-off-by: Macpaul Lin <[email protected]>
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Removed boot_flash_* extern variables.
boot_flash_type was totally unused. The other ones were actually constants, so
they have been replaced with #defines in the board config files.
Signed-off-by: Luca Ceresoli <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Sandeep Paulraj <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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Signed-off-by: Tom Warren <[email protected]>
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Signed-off-by: Tom Warren <[email protected]>
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Since addr_sp is a byte address, it should be adjusted by 12 here.
Signed-off-by: Eric Cooper <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Acked-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Tom Warren <[email protected]>
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Signed-off-by: Luca Ceresoli <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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CONFIG_OMAP34XX must be checked for existence, not value.
Signed-off-by: Luca Ceresoli <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Sandeep Paulraj <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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The reset sequence/configuration for ehci is highly board specific,
so this will be done in the source for the board, instead of
introducing several CONFIG_* which would be needed to make those
few lines in beagle.c usable across different OMAP boards.
Signed-off-by: Alexander Holler <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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Signed-off-by: Alexander Holler <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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Signed-off-by: Albert ARIBAUD <[email protected]>
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Fix include path of timer fttmr010 in a320evb.
Signed-off-by: Macpaul Lin <[email protected]>
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Move the header file and definitions of fttmr010
power control unit from a320 SoC folder to
"include/faraday" folder.
This change will let other SoC which also use fttmr010
could share the same header file.
Signed-off-by: Macpaul Lin <[email protected]>
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