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Add missing addresses to the list.
Signed-off-by: Michal Simek <[email protected]>
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Use full boot mode list in SPL.
Signed-off-by: Michal Simek <[email protected]>
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Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Reviewed-by: Peter Crosthwaite <[email protected]>
Reviewed-by: Nathan Rossi <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Setup half of memory from ram_size for ECC case.
All the time the same board can be configured
with or without ECC. Based on ECC case detection
use half of memory with the same configuration.
Signed-off-by: Michal Simek <[email protected]>
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Trivial patch.
Signed-off-by: Michal Simek <[email protected]>
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Added the lowlevel_init to enable the Neon instructions.
Initially the u-boot was causing undefined instruction
exception if loaded through tcl, and working fine if loaded
through FSBL. The exception was causing in convertion formula
of given time to ticks. It was because, the Neon instructions
were disabled and hence causing the undefined exception. In
FSBL case, the FSBL was enabling the Neon instructions. Hence,
added the lowlevel_init to enable the Neon instructions.
Also enable neon instructions for non-xilinx toolchain.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Acked-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Signed-off-by: Luka Perkov <[email protected]>
Acked-By: Prafulla Wadaskar <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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Add deep sleep support on Freescale LS1021QDS platform.
Signed-off-by: Tang Yuantian <[email protected]>
[York Sun: Fix conflict in fdt.c]
Reviewed-by: York Sun <[email protected]>
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This is now stored in the device tree.
Signed-off-by: Simon Glass <[email protected]>
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Add a hook to ensure that this information is saved.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The memory reference code takes a very long time to 'train' its SDRAM
interface, around half a second. To avoid this delay on every boot we can
store the parameters from the last training sessions to speed up the next.
Add an implementation of this, storing the training data in CMOS RAM and
SPI flash.
Signed-off-by: Simon Glass <[email protected]>
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Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.
Signed-off-by: Simon Glass <[email protected]>
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The existing IP checksum function is only accessible to the 'coreboot' cpu.
Drop it in favour of the new code in the network subsystem.
Signed-off-by: Simon Glass <[email protected]>
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As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are
only enabled in QSPI boot, and disabled in other boot modes.
IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot.
This patch will add fdt support for the above rules.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
S0 will cause CAAM self test failure. This patch is to enable snooping
for S0 slave interface. These CCI-400 operations are moved to
board_early_init_f() to be initialized earlier. For S4 slave interface,
issuing of snoop requests and DVM message requests are enabled.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Defining variable gic_dist_addr as a globe one prevents some
functions, which use it, from being used before relocation
which is the case in the deep sleep resume process on Freescale
SoC platforms.
Besides, we can always get the GIC base address by calling
get_gicd_base_address() without referring gic_dist_addr.
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Era property is added in the crypto node in device tree.
Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to
drivers/sec/sec.c so that it can be used across arm and
powerpc platforms having crypto node.
Signed-off-by: Ruchika Gupta <[email protected]>
[York Sun: Fix commit message indentation]
Reviewed-by: York Sun <[email protected]>
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If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>. As a result, all the SoCs that enable
CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they
do not support GPIO.
The right fix would be to split the lib/fdtdec.c to remove
dependency on GPIO.This commit adds a dummy <asm/arch/gpio.h>
to support OF_CONTROL for LS102x platform. This dummy header
will be removed after FDT-GPIO stuff is fixed correctly.
Signed-off-by: Ruchika Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and
CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will
be used via hwconfig.
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.
Signed-off-by: York Sun <[email protected]>
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Various minor code format issues are fixed in start16.S:
- U-boot -> U-Boot
- 32bit -> 32-bit
- Use TAB instead of SPACE to indent
- Move the indention location of the GDT comment block
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the support flag before accessing MTRR MSRs.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this
flag in x86_cpu_init_f() and save it in global data.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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arch/x86/cpu/mtrr.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Using coreboot-x86_defconfig, the following error occurred prior to this modification:
CC arch/x86/lib/interrupts
arch/x86/lib/interrupts.c: In function ‘do_irqinfo’:
arch/x86/lib/interrupts.c:134:24: error: iteration 16u invokes undefined behavior [-Werror=aggressive-loop-optimizations]
if (irq_handlers[irq].handler != NULL) {
^
arch/x86/lib/interrupts.c:133:2: note: containing loop
for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) {
^
cc1: all warnings being treated as errors
scripts/Makefile.build:275: recipe for target 'arch/x86/lib/interrupts.o' failed
make[1]: *** [arch/x86/lib/interrupts.o] Error 1
Makefile:1093: recipe for target 'arch/x86/lib' failed
make: *** [arch/x86/lib] Error 2
Change-Id: I3572a822081b72ab760f1eb99442e1161d3d167e
Signed-off-by: Sebastien Ronsse <[email protected]>
Acked-by: Simon Glass <[email protected]>
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We shouldn't assume that the VGA ROM can always be loaded at c0000. This
is only true on x86 machines.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Reinhard Arlt <[email protected]>
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This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Josef Wagner <[email protected]>
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This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <[email protected]>
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These boards are still non-generic boards.
It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.c
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Stefan Roese <[email protected]>
Cc: Andrea "llandre" Marson <[email protected]>
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This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <[email protected]>
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This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Ira W. Snyder <[email protected]>
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These boards are still non-generic boards:
P1011RDB, P1022RDB, P2010RDB, P2020RDB
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Poonam Aggrwal <[email protected]>
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These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Dave Liu <[email protected]>
Cc: Anton Vorontsov <[email protected]>
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PH1-sLD3, PH1-LD6b have DDR channel 2.
Signed-off-by: Masahiro Yamada <[email protected]>
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Match the suffixes of SG_MEMCONF_* macros with SZ_* macros defined
by <linux/sizes.h> for readability.
Signed-off-by: Masahiro Yamada <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler.
Signed-off-by: Masahiro Yamada <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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For PH1-Pro4, the bit 6 of the IECTRL must be set. It is the only
available bit in this register. There is no effect of the write
access to the other bits.
Signed-off-by: Masahiro Yamada <[email protected]>
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The assembly directive ".rept ... .endr" allows us to write the
init_page_table much shorter. To make things further simpler,
set the text and stack area as Normal Memory, and the other sections
as Device attribute.
Signed-off-by: Masahiro Yamada <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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