| Age | Commit message (Collapse) | Author |
|---|
|
|
|
For code archeologists, this is a nice example of copy and paste history.
Signed-off-by: Detlev Zundel <[email protected]>
Signed-off-by: Ben Warren <[email protected]>
|
|
Signed-off-by: Asen Dimov <[email protected]>
|
|
The QONG module can be downsized and delivered
with 128MB instead of 256MB. The patch adds
run time support for the two different memory
configurations.
Signed-off-by: Stefano Babic <[email protected]>
|
|
Add pin definitions ralted to the NAND controller to be used
to set up the pin multiplexer.
Signed-off-by: Stefano Babic <[email protected]>
|
|
The patch adds an accessor function to get the value of a gpio.
Signed-off-by: Stefano Babic <[email protected]>
|
|
Replace call to imx_get_mpllclk with imx_get_armclk
to show frequency of ARM core instead of mpll internal
bus in print_cpuinfo.
Signed-off-by: John Rigby <[email protected]>
CC: Stefano Babic <[email protected]>
|
|
The lowlevel_init file contained some hard-coded values
to setup the RAM. These board related values are moved into
the board configuration file.
Signed-off-by: Stefano Babic <[email protected]>
|
|
Signed-off-by: Heiko Schocher <[email protected]>
|
|
Because of s5pc1xx gpio is same as s5p seires SoC,
move gpio functions to drvier/gpio/
and modify structure's name from s5pc1xx_ to s5p_.
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Because of other s5p series SoC will use these serial functions,
modify function's name and structure's name.
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Signed-off-by: Alexander Holler <[email protected]>
|
|
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with
repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 85b3cce880a19e78286570d5fd004cc3cac06f57
Signed-off-by: Tom Rix <[email protected]>
|
|
|
|
|
|
|
|
|
|
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
determining of a device on SERDES is configured.
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Kim Phillips <[email protected]>
|
|
Signed-off-by: Lan Chunhe <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
|
|
clean up the wrong io_sel for PCI express according to latest manual.
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
|
|
cpu.c: In function 'checkcpu':
cpu.c:47: warning: unused variable 'gur'
Signed-off-by: Kumar Gala <[email protected]>
|
|
Signed-off-by: Kumar Gala <[email protected]>
|
|
Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
|
|
add the macro definition for Rtt_Nom termination value for DDR3
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
|
|
Added some needed fines and some misc additional defines
used by p4080 initialization.
Signed-off-by: Kumar Gala <[email protected]>
|
|
Extend pin control and clock control to GUTS memory map
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
|
|
When DDR is in synchronous mode, the existing code assigns sysclk
frequency to DDR frequency. It should be synchronous with the platform
frequency. CPU frequency is based on platform frequency in synchronous
mode.
Also fix:
* Fixes the bit mask for DDR_SYNC (RCWSR5[184])
* Corrects the detection of synchronous mode.
Signed-off-by: Srikanth Srinivasan <[email protected]>
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Ed Swarthout <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
|
|
This patch fixes error when CONFIG_SYS_NO_FLASH. And adds
nand flash and mmc initialization, which should go before
env initialization.
Signed-off-by: Thomas Chou <[email protected]>
Signed-off-by: Scott McNutt <[email protected]>
|
|
Global interrupt should be disabled from the beginning.
Signed-off-by: Thomas Chou <[email protected]>
Signed-off-by: Scott McNutt <[email protected]>
|
|
This function return cache-line aligned allocation which is mapped
to uncached io region.
Signed-off-by: Thomas Chou <[email protected]>
Signed-off-by: Scott McNutt <[email protected]>
|
|
This patch adds 64 bits swab support. Most 32 bits processors use
this. We need 64 bits swab for UBI.
Signed-off-by: Thomas Chou <[email protected]>
Signed-off-by: Scott McNutt <[email protected]>
|
|
This patch allow boards to override the default link script.
Signed-off-by: Thomas Chou <[email protected]>
Signed-off-by: Scott McNutt <[email protected]>
|
|
Add common post_word_load/post_word_store routines
for all mpc5121 boards. pdm360ng board POST support
added by subsequent patch needs them.
Signed-off-by: Anatolij Gustschin <[email protected]>
|
|
PDM360NG is a MPC5121E based board by ifm ecomatic gmbh.
Signed-off-by: Michael Weiss <[email protected]>
Signed-off-by: Detlev Zundel <[email protected]>
Signed-off-by: Anatolij Gustschin <[email protected]>
|
|
Configure CONFIG_SYS_MAX_RAM_SIZE address range in
DDR Local Access Window and determine the RAM size.
Fix DDR LAW afterwards using detected RAM size.
Signed-off-by: Anatolij Gustschin <[email protected]>
|
|
Signed-off-by: Anatolij Gustschin <[email protected]>
|
|
Signed-off-by: Anatolij Gustschin <[email protected]>
|
|
Extend mpc512x serial driver to support multiple PSC ports.
Subsequent patches for PDM360NG board support make use of this
functionality by defining CONFIG_SERIAL_MULTI in the board config
file. Additionally the used PSC devices are specified by defining
e.g. CONFIG_SYS_PSC1, CONFIG_SYS_PSC4 and CONFIG_SYS_PSC6.
Support for PSC devices other than 1, 3, 4 and 6 is not added
by this patch because these aren't used currently. In the future
it can be easily added using DECLARE_PSC_SERIAL_FUNCTIONS(N) and
INIT_PSC_SERIAL_STRUCTURE(N) macros in cpu/mpc512x/serial.c.
Additionally you have to add code for registering added
devices in serial_initialize() in common/serial.c.
Signed-off-by: Anatolij Gustschin <[email protected]>
|
|
Subsequent patch extends mpc512x serial driver to support
multiple PSC ports. The driver will provide an uninit()
function to stop the serial controller and to disable the
controller's clock. Adding uninit() entry to struct serial_device
allows disabling the serial controller after usage of
a stdio serial device.
This patch adds uninit() entry to the struct serial_device
and fixes initialization of this structure in the code
accordingly.
Signed-off-by: Anatolij Gustschin <[email protected]>
|
|
|
|
|
|
before, MPC8349ITX boots u-boot in 4.3sec:
column1 is elapsed time since first message
column2 is elapsed time since previous message
column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA: Configured for compact flash
0.032 0.000: I2C: ready
0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI: Bus Dev VenId DevId Class Int
2.652 0.011: 00 10 1095 3114 0180 00
2.652 0.000: PCI: Bus Dev VenId DevId Class Int
2.652 0.000: In: serial
2.652 0.000: Out: serial
2.652 0.000: Err: serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE: Bus 0: .** Timeout **
after, MPC8349ITX boots u-boot in 3.0sec:
0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA: Configured for compact flash
0.038 0.000: I2C: ready
0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI: Bus Dev VenId DevId Class Int
1.390 0.000: 00 10 1095 3114 0180 00
1.390 0.000: PCI: Bus Dev VenId DevId Class Int
1.400 0.010: In: serial
1.400 0.000: Out: serial
1.400 0.000: Err: serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE: Bus 0: .** Timeout **
also tested on these boards (albeit with a less accurate
boottime measurement method):
seconds: before after
8349MDS ~2.6 ~2.2
8360MDS ~2.8 ~2.6
8313RDB ~2.5 ~2.3 #nand boot
837xRDB ~3.1 ~2.3
also tested on an 8323ERDB.
v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).
Signed-off-by: Kim Phillips <[email protected]>
|
|
marketing didn't extend their postpend-with-an-A naming strategy
on rev.2's and higher beyond the first two 83xx families. This
patch stops us from misreporting we're running e.g., on an MPC8313EA,
when such a name doesn't exist.
Signed-off-by: Kim Phillips <[email protected]>
|
|
Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define
instead of a platform define. This will enable all the 83xx
platforms to use sdhc_clk based on CONFIG_FSL_ESDHC. It's
the same patch as commit 6b9ea08c5010eab5ad1056bc9bf033afb672d9cc
for the ppc/85xx.
Signed-off-by: Rini <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.
Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.
Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Wolfgang Denk <[email protected]>
Acked-by: Detlev Zundel <[email protected]>
Acked-by: Kim Phillips <[email protected]>
Cc: Peter Tyser <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
|
|
This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.
Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.
Signed-off-by: Stefan Roese <[email protected]>
|
|
Signed-off-by: Scott McNutt <[email protected]>
|
|
Merge cpu and lib cache code.
Flush cache before disabling.
Signed-off-by: Michal Simek <[email protected]>
|
|
There is used max cache size on system which doesn't define
cache size.
Signed-off-by: Michal Simek <[email protected]>
|
|
WB cache use different instruction that WT cache but the major code
is that same. That means that wdc.flush on system with WT cache
do the same thing as before.
You need newer toolchain with wdc.flush support.
Signed-off-by: Michal Simek <[email protected]>
|
