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Signed-off-by: Michael Krummsdorf <[email protected]>
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The device trees for TQMa6x SOM support variations in
- CPU type: imx6dl- or imx6q-
- MBa6 I2C bus access: -mba6a (i2c1) or -mba6b (i2c3)
(plus the respective common/module include trees)
- USBH1 is directly connected to a hub
- USBOTG is connected to a separate connector
and can act as host/device or full OTG port.
Signed-off-by: Michael Krummsdorf <[email protected]>
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The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Co-developed-by: Filip Brozović <[email protected]>
Signed-off-by: Bernhard Messerklinger <[email protected]>
Signed-off-by: Filip Brozovic <[email protected]>
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LDO mode may be already enabled by the ROM and enabling it again
can cause U-Boot to hang.
Avoid this problem by only enabling LDO mode if it is initially disabled.
Reported-by: Jorge Ramirez-Ortiz <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Tested-by: Jorge Ramirez-Ortiz <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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These PMC0 definitions are already defined in the beginning
of the file, so remove the duplication.
Reported-by: Stefano Babic <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-arc
This is pretty minor set of changes mostly touching HSDK board:
* Enable on-chip reset controller on HSDK
* Add possibility to turn-on & off L2$ on more
recent ARC HS processors.
* AXI tunnel clock calculation on HSDK
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As the driver of on-chip reset controller became available
we are ready to enable it.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Signed-off-by: Alexey Brodkin <[email protected]>
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Force inlining of IOC related functions used in other cache
functions. This is preventive change.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Signed-off-by: Alexey Brodkin <[email protected]>
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Since version 3.0 ARC HS supports SL$ (L2 system level cache)
disable. So add support for SL$ disable/enable to code.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Signed-off-by: Alexey Brodkin <[email protected]>
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Functions for reading indexed values from device tree
Enhancements to 'dm' command
Log test enhancements and syslog driver
DM change to read parent ofdata before children
Minor fixes
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The patch adds helper functions to allow reading a single indexed u32
value from a device-tree property containing multiple u32 values, that
is an array of integers.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add test case to cover dev_read_u64 and dev_read_u64_default functions.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Currently we are not able to test reservations created by ft_board_setup().
Implement ft_board_setup() to create an arbitrary reservation and enable
OF_BOARD_SETUP.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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For testing the handling of memory reservations create a reserved-memory
node in sandbox.dts and sandbox64.dts.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Hitting Ctrl-C is a documented way to exit the sandbox, but it is not
actually equivalent to the reset command. The latter, since it follows
normal process exit, takes care to reset terminal settings and
restoring the O_NONBLOCK behaviour of stdin (and, in a terminal, that
is usually the same file description as stdout and stderr, i.e. some
/dev/pts/NN).
Failure to restore (remove) O_NONBLOCK from stdout/stderr can cause
very surprising and hard to debug problems back in the terminal. For
example, I had "make -j8" consistently failing without much
information about just exactly what went wrong, but sometimes I did
get a "echo: write error". I was at first afraid my disk was getting
bad, but then a simple "dmesg" _also_ failed with write error - so it
was writing to the terminal that was buggered. And both "make -j8" and
dmesg in another terminal window worked just fine.
So install a SIGINT handler so that if the chosen terminal
mode (cooked or raw-with-sigs) means Ctrl-C sends a SIGINT, we will
still call os_fd_restore(), then reraise the signal and die as usual
from SIGINT.
Before:
$ grep flags /proc/$$/fdinfo/1
flags: 0102002
$ ./u-boot
# hit Ctrl-C
$ grep flags /proc/$$/fdinfo/1
flags: 0106002
After:
$ grep flags /proc/$$/fdinfo/1
flags: 0102002
$ ./u-boot
# hit Ctrl-C
$ grep flags /proc/$$/fdinfo/1
flags: 0102002
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The way the PCI nodes are written today causes a number of warnings if
we stop disabling some of the warnings we pass to DTC. As these
warnings aren't disabled in current Linux Kernel builds, we should aim
to not disable them here either, so rewrite these slightly. Update the
driver model doc as well.
Cc: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This file is potentially useful to other architectures saddled with ACPI
so move most of its contents to a common location.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Wolfgang Wallner <[email protected]>
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This header relates to ACPI and we are about to add some more ACPI
headers. Move this one into a new directory so they are together.
The header inclusion in pci_rom.c is not specific to x86 anymore, so drop
the #ifdef CONFIG_X86.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Reviewed-by: Wolfgang Wallner <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Add a sandbox test for the basic ACPI functionality we have so far.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Wolfgang Wallner <[email protected]>
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Add the C version of this header. It includes a few Chrome OS bits which
are disabled for a normal build.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Wolfgang Wallner <[email protected]>
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With P2SB the initial BAR (base-address register) is set up by TPL and
this is used unchanged right through U-Boot.
At present the reading of this address is split between the ofdata() and
probe() methods. There are a few problems that are unique to the p2sb.
One is that its children need to call pcr_read32(), etc. which needs to
have the p2sb address correct. Also some of its children are pinctrl
devices and pinctrl is used when any device is probed. So p2sb really
needs to get its base address set up in ofdata_to_platdata(), before it is
probed.
Another point is that reading the p2sb BAR will not work if the p2sb is
hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI
enumeration.
Reading ofdata in ofdata_to_platdata() is the correct place anyway, so
this is easy to fix.
Move the code into one place and use the early-regs property in all cases
for simplicity and to avoid needing to probe any PCI devices just to read
the BAR.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Wolfgang Wallner <[email protected]>
Tested-by: Wolfgang Wallner <[email protected]>
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Some files are taken or modified from coreboot, but the files are
no-longer part of the coreboot project. Fix the wording in a few places.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Wolfgang Wallner <[email protected]>
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This device should use ready-gpios rather than ready-gpio. Fix it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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SPCR has no clue if the UART base clock speed is different to
the default one. However, the SPCR 1.04 defines baud rate 0 as
a preconfigured state of UART and OS is supposed not to touch
the configuration of the serial device.
Linux kernel supports that starting from v5.0, see commit
b413b1abeb21 ("ACPI: SPCR: Consider baud rate 0 as preconfigured state")
for the details.
Signed-off-by: Andy Shevchenko <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The LED labels do not match the silkscreen on the board, fix it.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Manivannan Sadhasivam <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Tom Rini <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
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Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp
specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT
introduced by the commit 535d76a12150 ("armv8: layerscape: Add TFABOOT
support").
This config CONFIG_TFABOOT is activated for the trusted boot chain,
when U-Boot is loaded by TF-A.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add DT entries, Kconfig entries and board-specific entries to configure
FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Patrice Chotard <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Define FMC2 base address, for use in board files, until there is an
actual FMC2 bus driver.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Patrice Chotard <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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- Misc enhancements to Clearfog, including board variant detection
(Joel)
- Misc enhancements to Turris Mox, including generalization of the
ARMADA37xx DDR size detection (Marek)
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In case when ARM Trusted Firmware changes the default address of PCIe
regions (which can be done for devices with 4 GB RAM to maximize the
amount of RAM the device can use) we add code that looks at how ATF
changed the PCIe windows in the CPU Address Decoder and changes given
device-tree blob accordingly.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Currently on Armada-37xx the mem_map structure is statically defined to
map first 2 GB of memory as RAM region, and system registers and PCIe
region device region.
This is insufficient for when there is more RAM or when for example the
PCIe windows is mapped to another address by the CPU Address Decoder.
In the case when the board has 4 GB RAM, on some boards the ARM Trusted
Firmware can move the PCIe window to another address, in order to
maximize possible usable RAM.
Also the dram_init and dram_init_banksize looks for information in
device-tree, and therefore different device trees are needed for boards
with different RAM sizes.
Therefore we add code that looks at how the ARM Trusted Firmware has
configured the CPU Address Decoder windows, and then we update the
mem_map structure and compute gd->ram_size and gd->bd->bi_dram bank
base addresses and sizes accordingly.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Move Armada-8k specific DRAM init code into armada-8k specific
directory.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Commit e8e9715df2d4 requires the USB3 regulator node to have the
enable-active-high property for the regulator to work properly. The
GPIO_ACTIVE_HIGH constant is not enough anymore.
Signed-off-by: Marek Behún <[email protected]>
Fixes: e8e9715df2d4 ("regulator: fixed: Modify enable-active-high...")
Reviewed-by: Stefan Roese <[email protected]>
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With recent changes to the mmc subsystem (chip detect code etc) update
the sdhci node of the Turris Mox device tree.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Add a unique entry for ClearFog Base variant, reflected in the board
name and adjusted SerDes topology.
Signed-off-by: Joel Johnson <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Using a consistent hardcoded MAC address from the DTS file causes
issues when using multiple devices on the same network segment.
Instead rely on environment configuration or random generation.
Signed-off-by: Joel Johnson <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Tested on Solidrun ClearFog Base. Table alignment was:
| Lane # | Speed | Type |
--------------------------------
| 0 | 3 | SATA0 |
| 1 | 0 | SGMII1 |
| 2 | 3 | SATA1 |
| 3 | 5 | USB3 HOST1 |
| 4 | 5 | USB3 HOST0 |
| 5 | 4 | SGMII2 |
--------------------------------
After the change, it's correctly aligned as:
| Lane # | Speed | Type |
--------------------------------
| 0 | 3 | SATA0 |
| 1 | 0 | SGMII1 |
| 2 | 5 | PCIe1 |
| 3 | 5 | USB3 HOST1 |
| 4 | 5 | PCIe2 |
| 5 | 0 | SGMII2 |
--------------------------------
Signed-off-by: Joel Johnson <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Update the RTC (Read Timing Control) values for PCIe memory wrappers
following an ERRATA (ERRATA# TDB). This means the PCIe accesses will
used slower memory Read Timing, to allow more efficient energy
consumption, in order to lower the minimum VDD of the memory. Will lead
to more robust memory when voltage drop occurs (VDDSEG)
The code is based on changes from Marvell's U-Boot, specifically:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Sort the Armada series dts in the Makefile alphabetically
prior to adding new board support.
Signed-off-by: Josip Kelečić <[email protected]>
Reviewed-by: Luka Kovacic <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Pull in changes that have been pending in our 'next' branch. This
includes:
- A large number of CI improvements including moving to gcc-9.2 for all
platforms.
- amlogic, xilinx, stm32, TI SoC updates
- USB and i2c subsystem updtaes
- Re-sync Kbuild/etc logic with v4.19 of the Linux kernel.
- RSA key handling improvements
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Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
to enable cache driver in SPL.
This fixed error below in SPL:
cache controller driver NOT found!
Signed-off-by: Ley Foon Tan <[email protected]>
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Update these 3 files from Linux:.
- socfpga_arria10.dtsi (Commit ID c1459a9d7e92)
- socfpga_arria10_socdk.dtsi (Commit ID d9b9f805ee2b)
- socfpga_arria10_socdk_sdmmc.dts (Commit ID 17808d445b6f)
Change in socfpga_arria10.dtsi:
- Add clkmgr label, so that can reference to it in u-boot.dtsi.
Change in socfpga_arria10-u-boot.dtsi:
- Add compatible and altr,sysmgr-syscon for uboot.
Signed-off-by: Ley Foon Tan <[email protected]>
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Move Uboot specific properties to *u-boot.dtsi files.
Preparation to sync Arria 10 device tree from Linux.
Signed-off-by: Ley Foon Tan <[email protected]>
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Add and enable RTC-backed boot counter on ABB SECU1 platform.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Ley Foon Tan <[email protected]>
Cc: Simon Goldschmidt <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
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Align Kconfig and Kbuild logic to Linux 4.19 release with minimal impact
on files outside of this scope.
Our previous Kconfig sync was done by commit 5972ff077e0f ("kconfig /
kbuild: re-sync with Linux 4.18").
In this particular re-sync in order to keep clang support working a
number of related changes needed to be pulled in that had been missed
previously. Not all of these changes we easily traceable and so have
been omitted from the list below.
The imported Linux commits are:
[From prior to v4.18]
9f3f1fd29976 kbuild: Add __cc-option macro
d7f14c66c273 kbuild: Enable Large File Support for hostprogs
6d79a7b424a5 kbuild: suppress warnings from 'getconf LFS_*'
24403874316a Shared library support
86a9df597cdd kbuild: fix linker feature test macros when cross compiling with Clang
0294e6f4a000 kbuild: simplify ld-option implementation
[From v4.18 to v4.19]
96f14fe738b6 kbuild: Rename HOSTCFLAGS to KBUILD_HOSTCFLAGS
10844aebf448 kbuild: Rename HOSTCXXFLAGS to KBUILD_HOSTCXXFLAGS
b90a368000ab kbuild: Rename HOSTLDFLAGS to KBUILD_HOSTLDFLAGS
8377bd2b9ee1 kbuild: Rename HOST_LOADLIBES to KBUILD_HOSTLDLIBS
f92d19e0ef9b kbuild: Use HOST*FLAGS options from the command line
4ab3b80159d4 kconfig: check for pkg-config on make {menu,n,g,x}config
693359f7ac90 kconfig: rename SYMBOL_AUTO to SYMBOL_NO_WRITE
f60b992e30ff kbuild: replace $(LDFLAGS) $(ldflags-y) with $(ld_flags)
2fb9279f2c3e kbuild: change ld_flags to contain LDFLAGS_$(@F)
c931d34ea085 arm64: build with baremetal linker target instead of Linux when available
5accd7f3360e kconfig: handle format string before calling conf_message_callback()
a2ff4040151a kconfig: rename file_write_dep and move it to confdata.c
0608182ad542 kconfig: split out useful helpers in confdata.c
adc18acf42a1 kconfig: remove unneeded directory generation from local*config
79123b1389cc kconfig: create directories needed for syncconfig by itself
16952b77d8b5 kconfig: make syncconfig update .config regardless of sym_change_count
d6c6ab93e17f kbuild: remove deprecated host-progs variable
56869d45e364 kconfig: fix the rule of mainmenu_stmt symbol
c151272d1687 kconfig: remove unused sym_get_env_prop() function
1880861226c1 kconfig: remove P_ENV property type
e3fd9b5384f3 scripts/dtc: consolidate include path options in Makefile
4bf6a9af0e91 kconfig: add build-only configurator targets
f1575595d156 kconfig: error out when seeing recursive dependency
5e8c5299d315 kconfig: report recursive dependency involving 'imply'
f498926c47aa kconfig: improve the recursive dependency report
98a4afbfafd2 kconfig: fix "Can't open ..." in parallel build
9a9ddcf47831 kconfig: suppress "configuration written to .config" for syncconfig
87a32e624037 kbuild: pass LDFLAGS to recordmcount.pl
d503ac531a52 kbuild: rename LDFLAGS to KBUILD_LDFLAGS
217c3e019675 disable stringop truncation warnings for now
bc8d2e20a3eb kconfig: remove a spurious self-assignment
fd65465b7016 kconfig: do not require pkg-config on make {menu,n}config
5a4630aadb9a ftrace: Build with CPPFLAGS to get -Qunused-arguments
Note that this adds new cleanup work to do in that we should adapt the
shared library support we have to what is now upstream.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
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- doc: fix code examples in qemu-mips.rst
- mips: vcoreiii: fix memtest and cache coherency issues
- cmd/go: fix cache coherency issues on MIPS
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The FIT config node has reversed ATF and u-boot: ATF is set to 'firmware' but
u-boot is set to 'loadables'.
This script can work previously because spl fit driver wrongly appends fdt to
all loadable images. With the issue fixed in commit 9d15d1d1c24f ("Revert
"common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled"") the
u-boot in 'loadables' does not have fdt appended and fails to work. So correct
the script by moving u-boot to 'firmware' and ATF to 'loadables'.
Signed-off-by: Ye Li <[email protected]>
Reported-by: Matt Porter <[email protected]>
Tested-by: Matt Porter <[email protected]>
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It has been noticed on MT7628/88 platforms, that booting the RAM image
does not work reliably. Sometimes it works and sometimes not. Debugging
showed that this "might" be a cache related issue as very strange
errors occurred (e.g. output corrupted etc).
This patch adds a cache flush for the complete SDRAM area to the go cmd
before jumping to the entry point for the MIPS architecture. The
complete area is flushed as we don't know at this point, how big the
area of the "application" really is.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Tested-by: Mauro Condarelli <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Cc: Mauro Condarelli <[email protected]>
Cc: Weijie Gao <[email protected]>
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This patch fixes an stability issue seen on some vcoreiii targets,
which was root caused to a cache inconsistency situation.
The inconsistency was caused by having kuseg pointing to NOR area but
used as a stack/gd/heap area during initialization, while only
relatively late remapping the RAM area into kuseg position.
The fix is to initialize the DDR right after the TLB setup, and then
remapping it into position before gd/stack/heap usage.
Reported-by: Ramin Seyed-Moussavi <[email protected]>
Reviewed-by: Alexandre Belloni <[email protected]>
Reviewed-by: Horatiu Vultur <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
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