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Add a keyboard definition so that the keyboard can be used on pit.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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The device seems to hang in SPL if the full speed is used when booting from
USB, perhaps because the PMIC has not been set to the maximum ARM core
voltage yet. Slow it down to a reliable speed.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This commit allows to build Panasonic UniPhier family:
PH1-LD4, PH1-Pro4, PH1-sLD8
Signed-off-by: Masahiro Yamada <[email protected]>
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These are used by Panasonic UniPhier SoC family.
Signed-off-by: Masahiro Yamada <[email protected]>
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With some versions of gcc (that we know of 4.6.3 and 4.8.2 are affected)
it is necessary to specify --bss-plt to get the final blrl in the
_GOT2_TABLE_. Without this the last symbol does not get it's address
relocated. For the P2041RDB board this ended up being
NetArpWaitTimerStart which caused the ARP packets to timeout
immediately.
Signed-off-by: Joakim Tjernlund <[email protected]>
Signed-off-by: Chris Packham <[email protected]>
Acked-by: Joakim Tjernlund <[email protected]>
Acked-by: Scott Wood <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: York Sun <[email protected]>
CC: Alison Wang <[email protected]>
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Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Arnab Basu <[email protected]>
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DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).
Signed-off-by: York Sun <[email protected]>
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U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.
Signed-off-by: York Sun <[email protected]>
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This commit moves:
CONFIG_OF_CONTROL
CONFIG_OF_SEPARATE
CONFIG_OF_EMBED
CONFIG_OF_HOSTFILE
Because these options are currently not supported for SPL,
the "Device Tree Control" menu does not appear in the SPL
configuration.
Note:
zynq-common.h should be adjusted so as not to change the
default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Minkyu Kang <[email protected]>
Acked-by: Michal Simek <[email protected]>
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The macro MIN, MAX is defined as the aliase of min, max,
respectively.
Signed-off-by: Masahiro Yamada <[email protected]>
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Each CPU of PowerPC has its default linker script under the CPU
directory, except mpc8xx.
Every mpc8xx board has its own linker script under the board
directory, resulting in lots of duplication of linker scripts.
I notice eight mpc8xx boards have the same linker script.
We can decrease the number of linker scripts by putting a single
default linker script, arch/powerpc/cpu/mpc8xx/u-boot.lds.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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"0x00" is a valid serdes protocol for QorIQ parts, and can not be
used to test whether the serdes is enabled or disabled.
Signed-off-by: Ebony Zhu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Fix following issues in USB device-tree fixup:
- returns when either dr_mode or phy_type not defined.
This was terminating fix-up when only either property
was defined in hwconfig string
- updates dr_mode_type or dr_phy_type with junk value when
their index is -1. Now these are updated only when their
respective index is pointing to relevant types
in modes[] and phys[] array
- dr_mode_type and dr_phy_type were not NULL for
each controller
Signed-off-by: Ramneek Mehresh <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
Tested-by: Luka Perkov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Using CPU_HAS_PCR micro to present the SoC has pcr
(peripheral control register).
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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When use pcr (peripheral control register), then we won't need
to care about the peripheral ID.
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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Signed-off-by: Bo Shen <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.
Signed-off-by: Murali Karicheri <[email protected]>
Signed-off-by: Keegan Garcia <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
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At the high level, the problem is that we set gd multiple times (and
still do, even after the commit we're reverting). We set important
parts of gd to the copy which is not above stack but rather in the data
section. For the release, we're going to revert this change and for the
next release we shall correct things to only, really, set gd once to an
appropriate location and ensure that comments about it are correct too.
This reverts commit f0c3a6c4ad09210d5d4aeafe87685ee75e5683d6.
Acked-by: Albert Aribaud <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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We do not have to distinguish CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI
from CONFIG_TARGET_VEXPRESS_AEMV8A. Rename the former to the latter.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Steve Rae <[email protected]>
Cc: David Feng <[email protected]>
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Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.
We can delete the ones in arch and board Kconfig files.
This commit can be easily reproduced by the following command:
find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
N
s/\n[[:space:]]*string//
}
'
Signed-off-by: Masahiro Yamada <[email protected]>
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This commit adds the type definitions (+ help messages) of
CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} to arch/Kconfig,
which would save lots of type defs for taget boards.
(See also the next commit.)
Signed-off-by: Masahiro Yamada <[email protected]>
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The boards using CONFIG_SYS_DV_NOR_BOOT_CFG (i.e. calimain,
da850evm_direct_nor and enbw_cmc) had the _start symbol defined after
the CONFIG_SYS_DV_NOR_BOOT_CFG word rather than before it in
arch/arm/lib/vectors.S. Because of that, if by lack of luck
'gd->mon_len = (ulong)&__bss_end - (ulong)_start' (see setup_mon_len())
was a multiple of 4 kiB (see reserve_uboot()), then the last BSS word
overlapped the first word of the following reserved RAM area (or went
beyond the top of RAM without such an area) after relocation because
__image_copy_start did not match _start (see relocate_code()).
This was broken by commit 41623c9 'arm: move exception handling out of
start.S files', which defined _start twice (before and after the
CONFIG_SYS_DV_NOR_BOOT_CFG word), then by commit 0a26e1d 'arm: fix a
double-definition error of _start symbol', which kept the definition of
the _start symbol after the CONFIG_SYS_DV_NOR_BOOT_CFG word. This new
commit fixes this issue by restoring the original behavior, i.e. by
defining the _start symbol before the CONFIG_SYS_DV_NOR_BOOT_CFG word.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Manfred Rudigier <[email protected]>
Cc: Christian Riesch <[email protected]>
Cc: Sudhakar Rajashekhara <[email protected]>
Cc: Heiko Schocher <[email protected]>
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Some boards, like mx31pdk and tx25, require the beginning of the SPL
code to be position-independent. For these two boards, this is because
they use the i.MX external NAND boot, which starts by executing the
first NAND Flash page from the NFC page buffer. The SPL then needs to
copy itself to its actual link address in order to free the NFC page
buffer and use it to load the non-SPL image from Flash before running
it. This means that the SPL runtime address differs from its link
address between the reset and the initial copy performed by
board_init_f(), so this part of the SPL binary must be
position-independent.
This requirement was broken by commit 41623c9 'arm: move exception
handling out of start.S files', which used an absolute address to branch
to the reset routine. This new commit restores the original behavior,
which just performed a relative branch. This fixes the boot of mx31pdk
and tx25.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Reported-by: Helmut Raiger <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Magnus Lilja <[email protected]>
Cc: John Rigby <[email protected]>
Tested-by: Magnus Lilja <[email protected]>
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Commit 224beb833e544b802f08765271cec07667d39669 add clock
enabling function for FEC, but the masks are not available
for SX processor and the mx6sxsabresd cannot be built clean.
Signed-off-by: Stefano Babic <[email protected]>
CC: Fabio Estevam <[email protected]>
CC: Nikita Kiryanov <[email protected]>
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Some Tegra device tree files do not include information about the serial
ports. Add this and also add information about the input clock speed.
The console alias needs to be set up to indicate which port is used for
the console.
Also add a binding file since this is missing.
Series-changes; 5
- Add full serial port nodes from Linux tree (commit fc9d4dbe)
- Use /chosen/stdout-path instead of /aliases/console to specify the console
Signed-off-by: Simon Glass <[email protected]>
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If the sandbox device tree is provided to U-Boot (with the -d flag) then it
will use the device tree version in preference to the built-in device. The
only difference is the colour.
Signed-off-by: Simon Glass <[email protected]>
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This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass <[email protected]>
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Let PCI on mx6solox also be supported.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Introduce a structure for accessing the General Power Controller block (GPC)
registers.
Signed-off-by: Fabio Estevam <[email protected]>
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Commit fa9c021632473 ("mx6: add example DTB for mx6qsabreauto") introduced
'imx6q-sabreauto.dts' but it adds no real value as the dts file only contains
the 'model' and 'compatible' strings.
After this commit the final binary is also changed from 'u-boot.imx' to
'u-boot-dtb.imx', which may confuse users.
So revert it until a more complete and useful device tree could be provided.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Otavio Salvador <[email protected]>
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Signed-off-by: Nikolay Dimitrov <[email protected]>
Cc: Stefano Babic <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
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The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.
But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.
Signed-off-by: Ye.Li <[email protected]>
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Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Simon Glass <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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Define get_cpu_type(). Reuse it in is_cpu_type().
Cc: Igor Grinberg <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.
This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware of the way the calculation
is performed.
Refactor the calculation.
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).
Configure MMDC for slow pd.
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Cc: Igor Grinberg <[email protected]>
Acked-by: Igor Grinberg <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
Acked-by: Tim Harvey <[email protected]>
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Bit 16 in mapsr register is in a reserved field. Don't write to it.
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Acked-by: Tim Harvey <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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No functional changes.
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Acked-by: Tim Harvey <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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Add macro which defines i2c_pads_info structs for multiple SoC types,
and a macro which selects the appropriate struct based on CPU type,
thus eliminating the need to manage multiple i2c pad configurations
manually when supporting multiple SoC types.
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Acked-by: Tim Harvey <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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