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Add ESPI controller DT node for T102x.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add ESPI slave node for P5040DS.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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Add ESPI controller DT node for P5040.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add ESPI slave node for P4080DS.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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Add ESPI controller DT node for P4080.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add ESPI slave node for P3041DS.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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Add ESPI controller DT node for P3041.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add ESPI slave node for P2041RDB.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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Add ESPI controller DT node for P2041.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add ESPI slave node for P2020RDB.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add ESPI controller DT node for P2020.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add ESPI slave node for P1020RDB.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add ESPI controller DT node for P1020.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add espi slave nodes to support t2080qds.
Signed-off-by: Chuanhua Han <[email protected]>
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add espi controller node to support t2080.
Signed-off-by: Chuanhua Han <[email protected]>
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Map all resource for R5 to operate properly.
The patch is done based on the commit 23f7b1a77602 ("armv7R: K3: am654:
Enable MPU regions") which also map the whole 4GB at first and then change
mapping for DDR.
Signed-off-by: Michal Simek <[email protected]>
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The patch does sed 's/SPL_FPGA_SUPPORT/SPL_FPGA/g' but also fixing Makefile
and zynqmp.c to simplify if/endif logic in zynqmp.c.
This change is mostly done to be able to use CONFIG_IS_ENABLED macro and
obj-$(CONFIG_$(SPL_)FPGA) in Makefile. For them symbols need to be in sync.
And removing one line from Topic Miami boards which is not needed because
symbol is not enabled via Kconfig.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add missing dependencies for DM_SPI_FLASH.
Kconfig reports it as:
WARNING: unmet direct dependencies detected for SPL_DM_SPI_FLASH
Depends on [n]: SPL [=n] && SPL_DM [=n]
Selected by [y]:
- ARCH_ZYNQMP [=y] && <choice> && SPL_DM_SPI [=y]
Signed-off-by: Michal Simek <[email protected]>
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It was protected just for SPL_OS_BOOT but this function is only called when
SPL_ATF is enabled that's why change macro name.
Signed-off-by: Michal Simek <[email protected]>
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Value of shunt resistor for INA226s that monitor VCCINT and VCC_SOC power
rails are incorrect. This patch corrects those values.
Signed-off-by: Saeed Nowshadi <[email protected]>
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There is 2nd pca9548 mux on I2C1 bus that controls SFP0, SFP1, and QSFP1
ports. Channel 0 and 1 are connected to J287 connector for SFP0 & SFP1, and
channel 2 is connected to J288 connector for QSFP1.
Signed-off-by: Saeed Nowshadi <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add read/write memory utilities for 16 and 32 bits. Add these
api's for both little and big endian systems similar to arm
architecture.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Do not source xilinx board Kconfig by other boards. These configs should be
available only when Xilinx platforms are selected.
Signed-off-by: Michal Simek <[email protected]>
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- fix SPL image generation
- fix incorrect console output
- increase malloc_f and malloc_r space to fix LZMA decompression errors
- increase SPI flash clock
Signed-off-by: Mauro Condarelli <[email protected]>
[squashed to one patch, fix commit subject and description]
Signed-off-by: Daniel Schwierzeck <[email protected]>
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The GPIO bank name for banks J and K are not correct when using the
'gpio' command from the console.
The driver derives the bank name from the device tree instance string by
using the instance value and adding 'A': gpio0@xxaddrxx is Bank A,
gpio1@yyaddryy is Bank B and so on.
On the PIC32, there is no Bank I so instances 8 and 9 need to be
incremented as a minimum change.
An alternative (less opaque) implementation would be to use a bank-name
property instead but this would require modifying the driver code too.
Signed-off-by: John Robertson <[email protected]>
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GPIO state cannot be changed via the device tree (e.g. with gpio-hog) or
using the 'gpio' command from the console.
The root cause is a discrepancy between the driver and the device tree:
the driver code expects an absolute I/O address in the <reg> property,
while the device tree defines the address relative to a declaration in
the parent pinctrl node.
Changing the device tree to fix a driver issue would normally be wrong,
however:
- I have run the first version of U-Boot in which this driver appears
(v2016.03) and the same problem exists, so this is not a regression;
- There is no code that references a parent device tree node that might
suggest the intent of the author was to parse the DT as it exists now;
- The equivalent Linux PIC32 GPIO driver also uses absolute addresses
for the GPIO <reg> property. This change brings the U-Boot DT more
into line with Linux.
Additionally, the data sheet (Microchip ref. 60001361H) shows that the
register set to control a GPIO bank spans 0xE0 bytes, but the device
tree specified size is only 0x48 bytes.
Signed-off-by: John Robertson <[email protected]>
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Signed-off-by: John Robertson <[email protected]>
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The PIC32MZ DA Starter Kit does not need the card detect workaround
because the SDCD signal line is connected properly. Disable the
workaround in this case.
Signed-off-by: John Robertson <[email protected]>
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Add boolean input argument @no_map to helper function
fdtdec_add_reserved_memory() to add or not "no-map" property
for an added reserved memory node.
Property no-map is used by the Linux kernel to not not map memory
in its static memory mapping. It is needed for example for the|
consistency of system non-cached memory and to prevent speculative
accesses to some firewalled memory.
No functional change. A later change will update to OPTEE library to
add no-map property to OP-TEE reserved memory nodes.
Signed-off-by: Etienne Carriere <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add a special help message pointing to the relevant README.
Signed-off-by: Simon Glass <[email protected]>
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At present 64-bit sunxi boards use the Makefile to create a FIT, using
USE_SPL_FIT_GENERATOR. This is deprecated.
Update sunxi to use binman instead.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Heinrich Schuchardt <[email protected]>
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Linking a U-Boot larger than 1MB fails with PIE enabled:
u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation
truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__rel_dyn_end'
defined in .bss_start section in u-boot.
This extends the supported range by using adrp & add to load symbols
early while starting up.
Signed-off-by: Edgar E. Iglesias <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Tested-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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PIE requires a 4K aligned load address. If this is not met, trap
the startup sequence in a WFI loop rather than running into obscure
failures.
Tested-by: Michal Simek <[email protected]>
Suggested-by: André Przywara <[email protected]>
Signed-off-by: Edgar E. Iglesias <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Mention the requirement of 4K aligned load addresses in the
help section for the POSITION_INDEPENDENT option.
Suggested-by: Michal Simek <[email protected]>
Signed-off-by: Edgar E. Iglesias <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Atmel PIT timer is not available for next products that
have another timer hardware block.
To be able to use the common at91 code, guard the code that uses PIT
by ifdefs.
Signed-off-by: Eugen Hristev <[email protected]>
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We already have a function to retrieve the mac address from one EEPROM.
For boards with a second Ethernet interface, however, we would
require another EEPROM with a second unique MAC address.
Introduce at91_set_eth1addr which will look for a second EEPROM
and set the 'eth1addr' variable with the obtained MAC address.
Signed-off-by: Eugen Hristev <[email protected]>
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- Add error tracing messages to the generic PHY infrastructure
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Merge in v2020.10-rc5
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Add a missing memset to acpi_create_spcr().
The other acpi_create_xxxx() functions perform a memset on their
structures, acpi_create_spcr() does not and as a result the contents of
this table are partly uninitialized (and thus random after every reset).
Fixes: b288cd960072 ("x86: acpi: Generate SPCR table")
Signed-off-by: Wolfgang Wallner <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
[bmeng: fix the tags format in the commit message]
Signed-off-by: Bin Meng <[email protected]>
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Currently, the calculation for the length of the DSDT table includes any
bytes that are added for alignment, but those bytes are not initialized.
This is because the DSDT length is calculated after a call to
acpi_inc_align(). Split this up into the following sequence:
* acpi_inc()
* Calculate DSDT length
* acpi_align()
Signed-off-by: Wolfgang Wallner <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The term eMMC is used inconsistently within the FSP devicetree
bindings (e-mmc and emmc), especially for "emmc-host-max-speed"
documentation and code disagree.
Change all eMMC instances within the FSP bindings to consistently
use "emmc". The term "emmc" is already used a lot within U-Boot,
while "e-mmc" is only used in the FSP bindings.
Signed-off-by: Wolfgang Wallner <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
[bmeng: correct one typo in the commit message]
Signed-off-by: Bin Meng <[email protected]>
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There are drivers to support built in USB controller and PHY-s now, so lets add the USB nodes to DTSI.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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Since we have a driver for the reset controller, lets add the necessary node.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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There is already existing driver for SMEM so lets enable it for IPQ40xx as well.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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Its common to use dt-bindings instead of hard-coding clocks or resets.
So lets use the imported Linux GCC bindings on IPQ40xx target.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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The Toradex product is called apalis-imx8 consisting of SoM with
i.MX8QM and i.MX8QP SoCs.
Signed-off-by: Philippe Schenker <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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The Toradex product is called colibri-imx8x consisting of SoM with
i.MX8QXP and i.MX8DX SoCs.
Signed-off-by: Philippe Schenker <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration
code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs
have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8.
Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX")
Signed-off-by: Marek Vasut <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so
update u-boot to remove decoding and support for those parts.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add missed return
Signed-off-by: Peng Fan <[email protected]>
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