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To allow a TPL and SPL to run from different addresses/memories, we
need to split setup of the TPL and SPL stacks. To do so, we introduce
CONFIG_TPL_STACK (not listed in Kconfig) which can be used to override
the initial stack pointer for TPL.
To provide backward compatibility for existing boards, this is added
as an optional configuration item and the normal search order (i.e.
SPL_STACK, then SYS_STACK) apply if not defined.
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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TPL builds today don't need to call into firmware or set up the MMU
(if this changes, it should be controlled through a config option
whether to include this or not), but include the needed support code
for this anyway. By moving these unused low-level functions into
seperate function-sections, the linker can garbage-collect the unused
sections.
Note that (if DM support is enabled), there will be a call to the
cache-flushing code from alloc_priv(...) in drivers/core/device.c.
This then add 52 bytes of binary size (an increase from 20589 to 20641
bytes) compared to completely removing this code.
Even for a feature-rich TPL (including DM support as for the RK3368),
this equates to a size difference of significantly more than 10% in
TPL binary size.
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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With the finer-grained control over LIBCOMMON_SUPPORT for TPL/SPL (i.e.
with the newly introduced distinction between TPL_LIBCOMMON_SUPPORT and
SPL_LIBCOMMON_SUPPORT), we can simplify the #ifdef-check to simply use
CONFIG_IS_ENABELD.
Signed-off-by: Philipp Tomsich <[email protected]>
[fixed up to use 'puts' and LIBCOMMON:]
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The back-to-bootrom option is rather unfortunately named
CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM
instead of
CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM
To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM),
we need to rename it. At the same time, we introduce a TPL_ variant of
the option to give us finer-grained control over when it should be used.
This change is motivated by our RK3368 boot process, which returns to
the boot ROM only from the TPL stage, but not from the SPL stage.
Signed-off-by: Philipp Tomsich <[email protected]>
[added fix-up for evb-rk3229_defconfig and phycore-rk3288_defconfig:]
[fixed inverted CONFIG_IS_ENABLED test for rk3288:]
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
include/configs/rock.h: undef
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The back-to-bootrom support for Rockchip is equivalent to an
(assembly) implementation of setjmp/longjmp (i.e. it saves the
stack-pointer, link-register and callee-saved registers). Up until
now, this had only been implemented for AArch32 (i.e. ARMv7 or older),
which puts the new ARMv8 devices (which boot in AArch64 mode) at a
slight disadvantage.
To allow use of the 'back-to-bootrom' feature on new devices (e.g. the
RK3368), this commit adds an implementation for AArch64.
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Some devices (e.g. the RK3368) have only limited SRAM, but provide
support for loading the next boot stage after our SPL performs basic
setup (e.g. DRAM).
For target systems like these, we add a boot device BOOTROM that will
invoke a board-specific hook to return to the bootrom (if supported).
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x01)
is always false.
This does not match the comment
/*Wait till that bit clears*/
The problem was indicated by cppcheck.
I do not have the hardware to test if the code change below
leads to a correct system behavior.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Fixes: 00bbe96ebabb ("arm: omap: Unify get_device_type() function")
The control status register value is embedded in a structure somewhere
in SRAM, with the last refactoring effort. This patch allows OMAP3 EVM
(TMDSEVM3530) to boot again using the known control register base and
offset for 'readl', for the OMAP34XX case.
Signed-off-by: Derald D. Woods <[email protected]>
[trini: Change to if/else, add comment about it.]
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_NAND
Signed-off-by: Adam Ford <[email protected]>
[trini: Sync up a few more, add imply's]
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_ZBOOT
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_SPL
Note that trats does not actually use SPL, so this option can no-longer be
set.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_SH_ZIMAGEBOOT
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_SF_TEST
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_SAVES
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This patch converts CONFIG_CMD_REGINFO to Kconfig
Signed-off-by: Christophe Leroy <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_PCI
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This converts the following to Kconfig:
CONFIG_CMD_PCA953X
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Synced ohci0 and ehci0 nodes from Linux for sun50i-a64.dtsi
Here is the Linux last merge tag details:
Merge: 0e91f43d e5770b7
Author: Stephen Rothwell <[email protected]>
Date: Fri Jun 9 14:59:55 2017 +1000
Merge remote-tracking branch 'staging/staging-next'
Signed-off-by: Jagan Teki <[email protected]>
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The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls
the access to some clock/power related registers in PRCM.
Current Linux kernel will access the CPUS (AR100) clock in the PRCM
block, so the PRCM should be switched to non-secure.
Add code to switch the PRCM to non-secure.
Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.
Add the definition of this register and its bits in the PRCM header
file.
Signed-off-by: Icenowy Zheng <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The node name for the power seq pin is mmc2@0 like the mmc2_pins_a one.
This makes the original node (mmc2_pins_a) scrapped out of the dtb and
result in a unusable eMMC if U-Boot didn't configured the pins to the
correct functions.
Signed-off-by: Emmanuel Vadot <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Olliver Schinagl <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This converts the following to Kconfig:
CONFIG_SYS_I2C_OMAP24XX
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Signed-off-by: Rajat Srivastava <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: yinbo.zhu <[email protected]>
[YS: Revise subject, remove commit message]
Reviewed-by: York Sun <[email protected]>
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It is derived from Platform clock instead of Platform PLL frequency.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The driver is for all boards 24XX and up, so let's eliminate the
extra option called CONFIG_SYS_I2C_OMAP34XX since the driver checks
for CONFIG_OMAP34XX we don't need CONFIG_SYS_I2C_OMAP34XX.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Reviewed-by: Joe Hershberger <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When CONFIG_EFI_PARTITION is not set, the following build error is
seen in arch/x86/lib/acpi_s3.c:
error: expected declaration specifiers or '...' before '*' token
static void asmlinkage (*acpi_do_wakeup)(void *vector) = (void*)WAKEUP_BASE;
This is actually caused by missing asmlinkage declaration, but with
CONFIG_EFI_PARTITION on, the declaration comes from part.h which
is included from common.h.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Neither new design uses ISA bus, nor does any U-Boot codes use these
codes. Remove them.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Alexandru Gagniuc <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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move to Kconfig:
CONFIG_BCM_SF2_ETH
CONFIG_BCM_SF2_ETH_DEFAULT_PORT
CONFIG_BCM_SF2_ETH_GMAC
Also modified defconfigs of all platforms that use these configs.
Signed-off-by: Suji Velupillai <[email protected]>
Tested-by: Suji Velupillai <[email protected]>
Reviewed-by: JD Zheng <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
Signed-off-by: Steve Rae <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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fix the following compilation error reported by buidlman:
arm: + stm32f429-discovery
+arch/arm/mach-stm32/stm32f4/soc.c: In function 'arch_cpu_init':
+arch/arm/mach-stm32/stm32f4/soc.c:30:2: error: 'for' loop initial declarations are only allowed in C99 or C11 mode
+ for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
+ ^
+arch/arm/mach-stm32/stm32f4/soc.c:30:2: note: use option -std=c99, -std=gnu99, -std=c11 or -std=gnu11 to compile your code
+make[3]: *** [arch/arm/mach-stm32/stm32f4/soc.o] Error 1
+make[2]: *** [arch/arm/mach-stm32/stm32f4] Error 2
+make[1]: *** [arch/arm/mach-stm32] Error 2
+make: *** [sub-make] Error 2
Signed-off-by: Patrice Chotard <[email protected]>
Acked-by: Vikas Manocha <[email protected]>
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Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update the configuration files to support the device tree and driver
model. The peripheral clock and pins configuration are handled by
the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Xilinx changes for v2017.09
Zynq:
- Add Z-Turn board support
fpga:
- Remove intermediate buffer from code
Zynqmp:
- dts cleanup
- change psu_init handling
- Add options to get silicon version
- Fix time handling
- Map OCM/TCM via MMU
- Add new clock driver
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With the changes to fdt_get_base_address() we need to modify the logic
in ft_verify_fdt() for how we check the validity of the CCSR address.
Tested-on: qemu-ppce500 -M mpc8544ds
Fixes: 336a44877af8 ("fdt: Correct fdt_get_base_address()")
Cc: York Sun <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.12-rc6,
commit 6f7da290413ba713f0cdd9ff1a2a9bb129ef4f6c . This includes both M3
and H3 ULCB and Salvator-X boards.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Add initial support for the R8A7795 and R8A7796 based ULCB board.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Add the PFC5 PUEN address and SSI SDATA4 bit offset into the
rcar-gen3-base.h .
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
include/configs/ls1046aqds.h
include/configs/ls1046ardb.h
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Add support for Phytec pfla02, equipped with NAND.
CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
CPU: Automotive temperature grade (-40C to 125C) at 31C
Reset cause: POR
I2C: ready
DRAM: 1 GiB
NAND: 2048 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected n25q128 with page size 256 Bytes, erase size 64 KiB, total
16 MiB
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Signed-off-by: Stefano Babic <[email protected]>
CC: Stefan Christ <[email protected]>
CC: Stefan Müller-Klieser <[email protected]>
CC: Christian Hemp <[email protected]>
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Modify chip_id() routine such that to handle based on
the current el. Also make it available even if FPGA is
not enabled in system such it can be used always.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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