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PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.
Signed-off-by: Chenhui Zhao <[email protected]>
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Udit Agarwal <[email protected]>
Tested-by: Vinitha Pillai <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add Kconfig option to support loading PPA header from eMMC/SD and
NAND Flash.
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Udit Agarwal <[email protected]>
Tested-by: Vinitha Pillai <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Lichee Pi Zero is a development board with a V3s SoC, which features
64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not
soldered in production batch), a 40-pin RGB LCD connector and some extra
pins available as 2.54mm pins or stamp holes.
Add support for it.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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As we have now V3s support in board code, the V3s DTSI file should also
be added.
Add also some CCU include headers to satisfy the DTSI file.
Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Basic U-Boot support is now present for V3s.
Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.
As the DRAM controller code needs a big refactor, the SPL support is
disabled in this version.
Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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- Use - instead of @ for OPP tables
- Add input-delay properties to Cadence eMMC nodes
- Restore full license text because code-diff is annoying
- Fix NAND compatible strings
Signed-off-by: Masahiro Yamada <[email protected]>
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The SCP (System Control Processor) or what we call STM (Stand-by
MPU) is integrated in LD4, Pro4, sLD8, LD6b, LD11, and LD20.
For these SoCs, show the information if STM is enabled.
Signed-off-by: Masahiro Yamada <[email protected]>
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This configuration is supposed to be used with ARM Trusted Firmware,
so the SYSTEM_RESET is implemented in BL31. Invoke PSCI instead of
U-Boot's own reset code because we need to coordinate with SCP
(System Control Processor) for the system-level power management.
Signed-off-by: Masahiro Yamada <[email protected]>
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Set the same PHY parameters as the Boot ROM uses.
Signed-off-by: Masahiro Yamada <[email protected]>
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This is needed for HDMI, which will be added later.
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Video driver for older Allwinner SoCs uses cfb console framework which
in turn uses struct ctfb_res_modes to hold timing informations. However,
DM video framework uses different structure - struct display_timing.
It makes more sense to convert lcdc to use new timing structure because
all new drivers should use DM video framework and older drivers might be
rewritten to use new framework too.
Signed-off-by: Jernej Skrabec <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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TCON unit has similar layout and functionality also on newer SoCs. This
commit splits out TCON code for easier reuse later.
Signed-off-by: Jernej Skrabec <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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The Bananapi M2 Ultra is the first publicly available development board
featuring the R40 SoC.
This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra,
as well as a defconfig for it.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
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The R40's CPU controls are a combination of sun6i and sun7i.
All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.
Last, the R40 does not have a secure SRAM block.
This patch adds a PSCI implementation for CPU bring-up and hotplug
for the R40.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
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The R40 has the CPUCFG block at the same address as the A20.
Fix it.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
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The R40 seems to have a variant of the memory controller found in
the H3 and A64 SoCs. Adapt the code for use on the R40. The changes
are based on released DRAM code and comparing register dumps from
boot0.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
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According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.
This patch enables it for all the PLLs.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
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The watchdog found on the R40 SoC is the older variant found on the A20.
Add the proper "#if defines" to make it work.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
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The R40 SoC uses the AXP221s in I2C mode to supply power.
Some regulator's common usages have changed, and also the recommended
voltage for existing usages have changed. Update the defaults to match.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
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The R40 is the successor to the A20. It is a hybrid of the A20, A33
and the H3.
The R40's PIO controller is compatible with the A20,
Reuse the A20 UART and I2C muxing code by adding the R40's macro.
The display pipeline is the newer DE 2.0 variant.
Block enabling video on R40 for now.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
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At present if the return to bootrom fails (e.g. because you are not using
the Rockchip's bootrom's pointer table in MMC) then the board prints
SPL message and hangs. Print a message first if we can, to help in
understanding what happened when it hangs.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
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Each call of va_start must be matched by a call of va_end.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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If the system is running PSCI firmware, the System Reset function
(func ID: 0x80000009) is supposed to be handled by PSCI, that is,
the SoC/board specific reset implementation should be moved to PSCI.
U-Boot should call the PSCI service according to the arm-smccc
manner.
The arm-smccc is supported on ARMv7 or later. Especially, ARMv8
generation SoCs are likely to run ARM Trusted Firmware BL31. In
this case, U-Boot is a non-secure world boot loader, so it should
not be able to reset the system directly.
Signed-off-by: Masahiro Yamada <[email protected]>
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Adjust ARM SMC Calling Convention code for U-Boot:
- Replace the license block with SPDX
- Change path to asm-offsets.h
- Define UNWIND() as no-op
- Add Kconfig entry
- Add asm-offsets
Signed-off-by: Masahiro Yamada <[email protected]>
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Imports ARM SMC Calling Convention code from Linux 4.11-rc6.
The files have been copied as follows:
[Linux] [U-Boot]
arch/arm/kernel/smccc-call.S -> arch/arm/cpu/armv7/smccc-call.S
arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S
arch/arm/include/asm/opcodes* -> arch/arm/include/asm/opcodes*
include/linux/arm-smccc.h -> include/linux/arm-smccc.h
Signed-off-by: Masahiro Yamada <[email protected]>
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At present on a cold reboot we must reset the CPU to get it to full speed.
With 64-bit U-Boot this happens in SPL. At present we print the banner
before doing this, the end result being that we print the banner twice.
Print the banner a little later (after the CPU is ready) to avoid this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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The Intel CPU name can have leading spaces. Remove them since they are not
useful.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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For E6500 cores, L2 cache has been used as init_ram. L1 cache is a
write through cache on E6500.If lines are not locked in both L1 and
L2 caches, crashes are observed during secure boot. This patch locks/
unlocks both L1 and L2 cache to prevent the crash.
Signed-off-by: Ruchika Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Current sysclk fixing would fix all clocks with 'fixed-clock' compatible.
This patch is to fix sysclk by path to avoid any incorrect fixing.
Signed-off-by: Yangbo Lu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Number of TZASC instances may vary across NXP SoCs.
So put TZASC configuration under instance specific defines.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Ashish Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Santan Kumar <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Use CONFIG_ARCH_LS1021A instead.
Signed-off-by: York Sun <[email protected]>
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Use CONFIG_ARCH_LS1043A instead.
Signed-off-by: York Sun <[email protected]>
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Use CONFIG_ARCH_LS2080A instead.
Signed-off-by: York Sun <[email protected]>
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- Add SD secure boot target for ls1046ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size
as header is appended to u-boot image. So header will also be
copied from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for the
header.
- Reduce the size of CAAM driver for SPL Blobification functions
and descriptors, that are not required at the time of SPL are
disabled. Further error code conversion to strings is disabled
for SPL build.
Signed-off-by: Vinitha Pillai <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Ruchika Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add NAND secure boot target for ls1043ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- MACRO for CONFIG_BOOTSCRIPT_COPY_RAM is enabled to copy Bootscript
from NAND to DDR. Offsets for Bootscript on NAND and DDR have been
also defined.
Signed-off-by: Vinitha Pillai <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Ruchika Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
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- Add SD secure boot target for ls1043ardb.
- Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream
ID and corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for secure
boto header.
- Error messages during SPL boot are limited to error code numbers
instead of strings to reduce the size of SPL image.
Signed-off-by: Vinitha Pillai-B57223 <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Ruchika Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Define bootscript and its header addresses for QSPI target
Also add PPA header address in Kconfig
Signed-off-by: Vinitha Pillai <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Define bootscript and its header addresses for QSPI target. Also
define PPA header address to enable PPA validation.
Signed-off-by: Vinitha Pillai <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
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The header address of PPA defined in Kconfig.
Signed-off-by: Vinitha Pillai <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Reviewed-by: York Sun <[email protected]>
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BLOB feature is not required during SPL compilation.
Signed-off-by: Vinitha Pillai <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).
To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.
As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.
As the RK3399 needs to use its board_debug_uart_init() function, we
have Kconfig enable it by default for RK3399 builds.
With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB are then update (the change for the RK3399-Q7 is
left for later to not cause issues on applying the change).
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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For using mipi display, we need to enable lcd3v3
which supplied by rk808,so enable rk808 first.
Signed-off-by: Eric Gao <[email protected]>
Acked-by: Simon Glass <[email protected]>
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To enable mipi display, we need to enable pmic
rk808 first for lcd3v3 power,which use i2c0 to
communicate with soc. So enable i2c0.
Signed-off-by: Eric Gao <[email protected]>
Acked-by: Simon Glass <[email protected]>
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