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It also removes the ethernet pin configuration done during the board
initialization.
Signed-off-by: Vikas Manocha <[email protected]>
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And remove the uart pin configuration from board initialization.
Signed-off-by: Vikas Manocha <[email protected]>
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Signed-off-by: Vikas Manocha <[email protected]>
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Also created alias for usart1 and specified oscillator clock for stm32f7
discovery board.
Signed-off-by: Vikas Manocha <[email protected]>
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add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.
Signed-off-by: Vikas Manocha <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch cleans the code by using instructions allowed for armv7m as well as
other Arm archs.
Signed-off-by: Vikas Manocha <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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We only support cores that do Thumb-1 or later. So we add a comment to
explain this and remove the architecture test.
Cc: Albert ARIBAUD <[email protected]>
Cc: Mans Rullgard <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Commit 19a5944fcd62 ("mvgbe: remove setting of ethaddr within the
driver") removed the usage of get_random_hex() from the mvgbe driver
about six years ago. However the prototype of that function survived
till today in some kirkwood header file.
Remove that prototype and the CONFIG_MD5 dependency triggered by that.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Add usdhc4 node, which is eMMC for Engicam i.CoreM6 RQS modules.
eMMC Log:
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icorem6qdl-rqs> mmc dev 1
switch to partitions #0, OK
mmc1(part 0) is current device
icorem6qdl-rqs> mmcinfo
Device: FSL_SDHC
Manufacturer ID: fe
OEM: 14e
Name: MMC04
Tran Speed: 52000000
Rd Block Len: 512
MMC version 4.4.1
High Capacity: Yes
Capacity: 3.5 GiB
Bus Width: 4-bit
Erase Group Size: 512 KiB
HC WP Group Size: 4 MiB
User Capacity: 3.5 GiB
Boot Capacity: 16 MiB ENH
RPMB Capacity: 128 KiB ENH
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Reviewed by: Stefano Babic <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Boot from eMMC:
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U-Boot SPL 2017.01-00314-gd0cd9cd-dirty (Jan 25 2017 - 13:25:27)
Trying to boot from MMC2
U-Boot 2017.01-00314-gd0cd9cd-dirty (Jan 25 2017 - 13:25:27 +0100)
CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 36C
Reset cause: POR
Model: Engicam Is.IoT MX6UL eMMC Starterkit
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
switch to partitions #0, OK
mmc1(part 0) is current device
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Reviewed by: Stefano Babic <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Instead of initializing 'struct src' to SRC_BASE_ADDR on
every function better to have global define macro.
Reviewed by: Stefano Babic <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Use meaningful macros IMX6_BMODE_*, instead of numerical
number in boot mode detection code.
Cc: Tim Harvey <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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BOOT_CFG1[7:4] the NAND boot mode selection is done
only when BOOT_CFG1[7] is 1 hence update the NAND
boot mode detection bit case. This information available
on Table 8-11. NAND Boot eFUSE Descriptions, from IMX6DQRM.
Cc: Tim Harvey <[email protected]>
Reviewed by: Stefano Babic <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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For i.MX6, the bootmode determine code is part of spl_boot_device,
but there is might be a possibility for other part the code need to
check the desired boot mode for adding new functionalities like
modeboot env variable, or changing boot order etc.
So introduced imx6_src_get_boot_mode which actually reading the
boot mode register for desired modes.
More cleanup will be add in future patches.
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Add NAND support for Engicam Is.IoT MX6UL board.
Cc: Stefano Babic <[email protected]>
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add FEC support for Engicam Is.IoT MX6UL module.
Cc: Stefano Babic <[email protected]>
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add FEC node for Engicam Is.IoT MX6UL module.
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add I2C support for Engicam Is.IoT MX6UL module.
isiotmx6ul> i2c bus
Bus 0: i2c@021a0000
Bus 1: i2c@021a4000
isiotmx6ul> i2c dev 0
Setting bus to 0
isiotmx6ul> i2c dev
Current bus is 0
isiotmx6ul> i2c speed 100000
Setting bus speed to 100000 Hz
isiotmx6ul> i2c probe
Valid chip addresses: 00 2C 44 78
isiotmx6ul> i2c md 2C 0xff
00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add I2C nodes for Engicam Is.IoT MX6UL module.
Cc: Stefano Babic <[email protected]>
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Boot from MMC:
-------------
U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33)
Trying to boot from MMC1
U-Boot 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33 +0100)
CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 33C
Reset cause: POR
Model: Engicam Is.IoT MX6UL Starterkit
DRAM: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
isiotmx6ul>
Cc: Stefano Babic <[email protected]>
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add EVK board support.
Add the evk dts file.
LOG:
U-Boot 2017.03-rc2-00038-gab86c1d (Feb 22 2017 - 15:59:58 +0800)
CPU: Freescale i.MX7ULP rev1.0 at 500 MHz
Reset cause: POR
Boot mode: Dual boot
Model: NXP i.MX7ULP EVK
DRAM: 1 GiB
MMC: FSL_SDHC: 0
In: serial@402D0000
Out: serial@402D0000
Err: serial@402D0000
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add i.MX7ULP dtsi file.
Add clock and pinfun header files.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF
size for HAB support boot on mx7ulp.
Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build
secure uboot.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Reviewed-by : Stefano Babic <[email protected]>
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Drop CONFIG_LPUART_32B_REG.
Move the register structure to a common file include/fsl_lpuart.h
Define lpuart_serial_platdata structure which includes the reg base and flags.
For 32Bit register access, use lpuart_read32/lpuart_write32 which handles
big/little endian.
For 8Bit register access, still use the orignal code.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by : Stefano Babic <[email protected]>
Cc: Bhuvanchandra DV <[email protected]>
Cc: York Sun <[email protected]>
Cc: Shaohui Xie <[email protected]>
Cc: Alison Wang <[email protected]>
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Add lpi2c driver for i.MX7ULP.
Need to enable the two options to use this driver:
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins
to add IOMUX_CONFIG_MPORTS flags.
Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not
aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address
to aligin with it.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Cc: Stefano Babic <[email protected]>
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Update the mxc_ocotp driver to support i.MX7ULP.
The read/write sequence has some changes due to
PDN and OUT_STATUS registers added and TIME register is
removed. Also update the bank size and number.
Add is_mx7ulp macro in sys_proto.h
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Reviewed-by : Stefano Babic <[email protected]>
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Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP.
Have added all ports on RGPIO2P_0 and RGPIO2P_1.
The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set
to y to enable the drivers.
To use the GPIO function, the IBE and OBE needs to set in IOMUXC.
We did not set the bits in driver, but leave them to IOMUXC settings
of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number
for gpio APIs access.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Reviewed-by : Stefano Babic <[email protected]>
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Implement the i2c clock enable and get function for mx7ulp. These
functions are required by imx_lpi2c driver.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Implement soc level functions to get cpu rev, reset cause, enable cache,
etc. We will disable the wdog and init clocks in s_init at very early u-boot
phase.
Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev
is hard coded to a fixed value. This may change in future.
Reuse some code in imx-common.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set
clock source, divider, clock rate and parent source.
Users need to include pcc.h to use the APIs to for peripherals clock. Each
peripheral clock is defined in enum pcc_clk type.
SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD
enablement and settings, and all SCG clock initialization. User need use enum
scg_clk to access each clock source.
In clock.c, we initialize necessary clocks at u-boot s_init and implement the
clock functions used by driver modules to operate clocks dynamically.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add a new driver under ULP directory to support its IOMUXC
controllers. The ULP has two IOMUXC, the IOMUXC0 is used
for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as
the default IOMUX in this driver. Any pins in IOMUXC0 needs
to configure with IOMUX_CONFIG_MPORTS in its mux_mode field.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by : Stefano Babic <[email protected]>
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Add imx-regs.h for i.MX7ULP registers addresses definitions and some
registers structures.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Reviewed-by : Stefano Babic <[email protected]>
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i.MX7ULP is a new series SoC which has different architecture
from previous i.MX platforms. Create a new cpu folder for it,
and add it to Kconfig.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Reviewed-by : Stefano Babic <[email protected]>
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Tinker board have a usb host. add dts node to provide power supply.
Signed-off-by: Eddie Cai <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Bind usb host and otg vbus to its source.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Enable gmac interface for rk3288 board dts.
use "okay" not "ok"
Signed-off-by: Jacob Chen <[email protected]>
Acked-by: Simon Glass <[email protected]>
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rk3036 support sdmmc, add dts node to support it.
Signed-off-by: Eddie Cai <[email protected]>
Acked-by: Simon Glass <[email protected]>
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add mmc alias for rk3399
Signed-off-by: Eddie Cai <[email protected]>
Acked-by: Simon Glass <[email protected]>
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evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: William Zhang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Add rk3328 pinctrl driver and grf/iomux structure definition.
Signed-off-by: William Zhang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Add rk3328 clock driver and cru structure definition.
Signed-off-by: William Zhang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
It supports two USB2.0 EHCI ports. Other interfaces are very
much like RK3288, the DRAM are 32bit width address and support
address from 0 to 4GB-16MB range.
Signed-off-by: William Zhang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error:
Signed-off-by: Simon Glass <[email protected]>
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Add dts binding header for rk3328, files origin from kernel.
Signed-off-by: William Zhang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Enable all the CONFIGs which need by SPL.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Added rockchip tag:
Drop CONFIG_ROCKCHIP_DWMMC for now due to build error:
Move changes to arch/arm/mach-rockchip/Kconfig to this patch:
Signed-off-by: Simon Glass <[email protected]>
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Add SPL support for rk3399, default with of-platdata enabled.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Drop Kconfig changes to fix build error:
Signed-off-by: Simon Glass <[email protected]>
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Add syscon and dmc node, and 'u-boot,dm-pre-reloc' option for
required driver.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Added rockchip tag:
Signed-off-by: Simon Glass <[email protected]>
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RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.
Signed-off-by: Kever Yang <[email protected]>
Added rockchip: tag:
Signed-off-by: Simon Glass <[email protected]>
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The rk3188 needs 3 U-Boot stages: a tpl living in 1KB of sram, a spl
the resides in the rest of the sram and loads the regular U-Boot living
in regular ram.
Signed-off-by: Heiko Stuebner <[email protected]>
Tested-by: Kever Yang <[email protected]>
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The sdram controller blocks are very similar to the rk3288 in utilizing
memory scheduler, Designware uPCTL and Designware PUBL blocks, only
limited to one bank instead of two.
There are some minimal differences when setting up the ram, so it gets
a separate driver for the rk3188 but reuses the driver structs, as there
is no need to define the same again.
More optimization can happen when the modelling of the controller parts
in the dts actually follow the hardware layout hopefully at some point
in the future.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Kever Yang <[email protected]>
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