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Enable the Ethernet device in DT, provide board-specific configuration,
and enable the driver in Kconfig.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Tegra186 includes a Synopsys DWC EQoS (Ethernet) device. Add this to the
Tegra186 SoC DT so that boards can make use of it.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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On Tegra186, the bootloader which runs before U-Boot passes the Ethernet
MAC address to U-Boot using device tree. Extract this value and write it
to the environment, so that the Ethernet uclass picks it up and uses it
for the built-in Ethernet device.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Extend the Tegra186 implementation of board_late_init() to call a per-SoC
"hook" function. This will allow SoC-specific (rather than Tegra-wide)
functionality to be implemented without the core Tegra code needing to be
aware of the details. While board186.c is currently only used for
Tegra186, it should be applicable to any other future SoC, and perhaps its
simple design could be back-ported to older SoCs in the future too.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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For 64-bit ARM systems we provide just a timer_read_counter()
implementation and rely on the generic non-uclass get_ticks() function
in lib/time.c to call the former.
However this function is actually not 64-bit safe, as it assumes a
"long" to be 32-bit. Beside the fact that the resulting uint64_t
isn't bigger than "long" on 64-bit architectures and thus combining two
counters makes no sense, we get all kind of weird results when we try
to OR in the high value shifted by _32_ bits.
So let's avoid that function at all and provide a straight forward
get_ticks() implementation for ARMv8, which also is in line with ARMv7.
This fixes occasional immediate time-out expiration issues I see on the
Pine64 board. The root cause of this needs to be investigated, but this
fix looks like the right thing anyway.
Signed-off-by: Andre Przywara <[email protected]>
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Cover-Letter: Fixes several spelling errors for the words "resetting",
"extended", "occur", and "multiple".
Signed-off-by: Vagrant Cascadian <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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SPL_MMC_SUPPORT defined in rockchip top level Kconfig instead of
inside rk3288 and default to disable if ROCKCHIP_SPL_BACK_TO_BROM
defined.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Since we implement the dram capacity auto detect, we don't
need to set the channel number and sdram-channel in dts.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Tested-by: Vagrant Cascadian <[email protected]>
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Add support for rk3288 dram capacity auto detect, support DDR3 and
LPDDR3, DDR2 is not supported.
The program will automatically detect:
- channel number
- rank number
- column address number
- row address number
The dts file do not need to describe those info after apply this patch.
Signed-off-by: Kever Yang <[email protected]>
Tested-by: Simon Glass <[email protected]>
Tested-by: Vagrant Cascadian <[email protected]>
Tested-by: Vagrant Cascadian <[email protected]>
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The GRF base address is missing, fix it.
Signed-off-by: Kever Yang <[email protected]>
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The Clock Multiplier in rk3399 EMMC programmable clock generator
is broken, we can remove its support from SoC GRF register.
Without this patch, rk3399 emmc driver is not work after below patch
applied:
6dffdbc mmc: sdhci: Add the programmable clock mode support
Signed-off-by: Kever Yang <[email protected]>
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This function is called from outside the driver. It should be placed into
common SoC code. Move it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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This function is called from outside the driver. It should be placed into
common SoC code. Move it.
Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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This function is called from outside the driver. It should be placed into
common SoC code. Move it.
Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Mostly by adding MACH_SUN50I to some existing #ifdefs enable support
for the the HCI0 USB host controller on the A64.
Fix up some minor 64-bit hiccups on the way.
Add the bare minimum DT bits to the A64 .dtsi and enable the controllers
and the PHY on the Pine64.
This is limited to the first USB controller at the moment, which is
connected to the lower USB socket on the Pine64 board.
[Andre: remove unneeded defines, enable OHCI, add commit message]
Signed-off-by: Amit Singh Tomar <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses
are at an offset of 0x200 within the SID address space.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
missing an alias entry to trigger the driver instantiation by U-Boot.
Add the line to point U-Boot to the Ethernet DT node.
This enables TFTP boot on the Pine64.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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CONFIG_SUNXI -> CONFIG_ARCH_SUNXI
and removed CONFIG_SUNIX from config_whitelist.txt
Cc: Simon Glass <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Hans de Goede <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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This is a cleaned up version set_pll() from Allwinner's boot0 source
(bootloader/basic_loader/bsp/bsp_for_a80/common/common.c).
[[email protected]: Added commit message; style cleanup]
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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Since the A80 has many cores which we intend to use in SMP fashion,
we should set the SMP bit for the boot CPU.
[[email protected]: Added commit message]
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all applications (e.g. headless
systems might want to give priority to IO modules).
Adding a common callout to gtbus_init() from the SPL clock init
with a weakly defined implementation in sunxi/clock.c to fallback
to for platforms that don't require this.
[[email protected]: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.
With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.
[[email protected]: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai <[email protected]>
[[email protected]: Drop some huge non-documenting #if 0 ... #endif blocks]
[[email protected]: Fix checkpatch warnings]
Signed-off-by: Hans de Goede <[email protected]>
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Introduce run-time DDR PHY training.
Signed-off-by: Masahiro Yamada <[email protected]>
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Add the LD11 SoC data and adjuts the printf() format because this is
a 64-bit SoC. Otherwise, 16-digits pointer addresses would break
the log format.
Signed-off-by: Masahiro Yamada <[email protected]>
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Do not hard-code the number of DX blocks because it is a different
value for LD11 SoC.
Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it
is the last user.
Signed-off-by: Masahiro Yamada <[email protected]>
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The DDR PHY register view of LD11 is slightly different from that
of LD4/Pro4/sLD8, but it will be possible to share the register
macros (and I want to re-use as much code as possible). Change
the code in the more flexible form.
Signed-off-by: Masahiro Yamada <[email protected]>
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The USB boot without the stand-by MPU is available on ES3 or later
of LD11 SoC, but the code in this if-conditional block must not be
run when booting from USB. Check if the boot device is USB, and
skip the code in the case.
Signed-off-by: Masahiro Yamada <[email protected]>
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At the moment, the clk driver is not clever enough to automatically
enable parent clocks like Linux. Enable the STDMAC clock explicitly
if USB is enabled.
Signed-off-by: Masahiro Yamada <[email protected]>
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The status register should be polled.
Signed-off-by: Masahiro Yamada <[email protected]>
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This PHY might be used for other SoCs in the future.
Avoid including the SoC name in the header name.
Signed-off-by: Masahiro Yamada <[email protected]>
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- Constify UMC setting data arrays
- Merge data arrays *_d0 and *_d1.
- Add PHY parameters for LD20 C1 board
Signed-off-by: Masahiro Yamada <[email protected]>
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After SoC evaluation, they turned out unnecessary.
Signed-off-by: Masahiro Yamada <[email protected]>
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For Electro-Magnetic Compatibility.
Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent.
Signed-off-by: Masahiro Yamada <[email protected]>
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This delay is already cared by the callers of this function.
Signed-off-by: Masahiro Yamada <[email protected]>
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The environment fdt_file is useful to remember the appropriate DTB
file name. Adjust it to the recent renaming in the upstream kernel.
Signed-off-by: Masahiro Yamada <[email protected]>
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Fix the warning from dtc like,
---8<----
Warning (unit_address_vs_reg): Node /ahb/apb/pmc@f0014000/periph64ck/sdmmc0_hclk has a reg or ranges property, but no unit name
--->8----
Signed-off-by: Wenyou Yang <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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add at least icache support for at91 based boards.
This speeds up NOR flash access on an at91sam9g15
based board from 15.2 seconds reading 8 MiB from
a SPI NOR flash to 5.7 seconds.
Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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on at91sam9x5 PRES offset is 4 in the PMC master
clock register.
Signed-off-by: Heiko Schocher <[email protected]>
Acked-by: Wenyou Yang <[email protected]>
Acked-by: Andreas Bießmann <[email protected]>
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add missing MPDDRC_MD defines
Signed-off-by: Heiko Schocher <[email protected]>
Acked-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
common/Kconfig
configs/dms-ba16_defconfig
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Add 'PCI' as a menu option and migrate all existing users.
Signed-off-by: Tom Rini <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
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i.CoreM6 Quad/Dual modules are system on module solutions
manufactured by Engicam with following characteristics:
CPU NXP i.MX6 DQ, 800MHz
RAM 1GB, 32, 64 bit, DDR3-800/1066
NAND SLC,512MB
Power supply Single 5V
MAX LCD RES FULLHD
and more info at
http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add imx6q pinctrl defines support from Linux.
Here is the last commit:
"ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ"
(sha1: d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2)
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add i.MX6Q dtsi support from Linux.
Here is the last commit:
"ARM: dts: add gpio-ranges property to iMX GPIO controllers"
(sha1: bb728d662bed0fe91b152550e640cb3f6caa972c)
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Matteo Lisi <[email protected]>
Cc: Michael Trimarchi <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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