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To increase readability, use the defined constant instead of specifying
SPCR[TBEN] as a number.
Reviewed-by: Sinan Akman <[email protected]>
Signed-off-by: J. Neuschäfer <[email protected]>
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Globals defined in headers can result in multiple-definition errors
while linking, if they are visible beyond the current translation unit.
This hasn't been a problem for initreg.h so far, but would become a
problem in the next patch, where I use a constant from initreg.h in a
second C file.
Reviewed-by: Sinan Akman <[email protected]>
Signed-off-by: J. Neuschäfer <[email protected]>
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and registers"
J. Neuschäfer <[email protected]> says:
This patchset changes the definition r0 etc. to %r0, so that the
assembler can check that registers are only used where expected, and
fixes the fallout.
Link: https://lore.kernel.org/r/[email protected]
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PowerPC general-purpose registers are historically specified as plain
numbers (0-31), which makes them hard to distinguish from immediates.
For this reason, include/ppc_asm.tmpl defines aliases named r0-r31.
This can still lead to uncaught mistakes if a register is used in place
of a number.
Instead of (e.g.) 5 use %r5, which will result in an assembler warning
if used as a number. Turn these warnings into errors by passing
`--fatal-warnings` to the assembler.
I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig
(MPC85xx) that this patch results in the same machine code.
Signed-off-by: J. Neuschäfer <[email protected]>
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Instructions such as dcbi are in the X-form; they have RA and RB fields
and the effective address (EA) is computed as (RA|0)+(RB). In words,
this means that if RA is zero, the left-hand side of the addition is
zero, otherwise the corresponding GPR is used. r0 can never be used on
the left-hand side of a X-form instruction.
For D-form instructions such as addis, the Power ISA illustrates this in
the instruction pseudo-code:
if RA = 0 then RT <- EXTS(SI || 0x0000)
else RT <- (RA) + EXIS(SI || 0x0000)
In all of these cases, RA=0 indicates the value zero, not register r0.
I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig
(MPC85xx) that this patch results in the same machine code.
Signed-off-by: J. Neuschäfer <[email protected]>
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lmb_reserve() is just calling lmb_reserve_flags() with LMB_NONE.
There's not much we gain from this abstraction.
So let's remove the latter, add the flags argument to lmb_reserve()
and make the code a bit easier to follow.
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Tested-by: Sam Protsenko <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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into next
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Describe APMU controller as a remoteproc device capable of starting
the Cortex-R52 cores in Renesas R8A779G0 V4H SoC DT. The APMU IP is
in fact a power management unit capable of additional operations, but
those are not used by U-Boot so far.
Signed-off-by: Marek Vasut <[email protected]>
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Add R-Car Gen4 APMU controller remoteproc driver capable of starting
the Cortex-R52 cores in Renesas R8A779G0 V4H/V4M SoC. The APMU IP is
in fact a power management unit capable of additional operations, but
those are not used by U-Boot so far.
This requires slight adjustment to the SPL entry point code, as that
is being executed on the Cortex-R52 #0 and the Cortex-R52 #0 enters an
endless loop once it starts the rest of the SPL on Cortex-A76 core.
The endless loop now checks for content of APMU CRBARP registers and
tests whether valid VLD_BARP and BAREN_VALID bits are set, if so, the
Cortex-R52 core exits the endless loop and jumps to address started
in CRBARP[31:18] register in ARM mode, which is a trampoline code to
jump to the final entry point.
The trampoline code is in place to avoid limitation of CRBARP[31:18]
address field, which limits the core start address to memory addresses
aligned to 0x40000 or 256 kiB . The trampoline is placed at 0x40000
aligned address and jumps to the final entry point, which can be at
an address with arbitrary alignment at instruction granularity.
Signed-off-by: Marek Vasut <[email protected]>
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This DTC_FLAGS assignment is no longer necessary as all R-Car Gen2/Gen3/Gen4
platforms have been converted to OF_UPSTREAM and matching DTC_FLAGS assignment
is present in dts/upstream/src/arm64/Makefile . Drop the remnant.
Signed-off-by: Marek Vasut <[email protected]>
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Align R-Car Gen2/Gen3/Gen4 configuration header file to look
basically the same way across these three SoC generations.
There are subtle difference between the remaining bits in
those files across SoC generations, but the common bits are
now aligned. There is not much left in those headers either,
most of the configuration is now converted to Kconfig.
Specifically for R-Car Gen3, GIC registers have been moved
to architecture specific header file rcar-gen3-base.h , the
rest of the changes here are comment changes and indentation
changes.
Signed-off-by: Marek Vasut <[email protected]>
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Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC.
The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts
U-Boot proper on the Cortex-A76 core.
The SoC BootROM can not boot the CA76 core directly, instead the SPL starts
on the CR52 core which immediately brings up the CA76 core, which in turn
starts executing the actual SPL. This is achieved by placing a tiny bit of
precompiled Aarch32 code at the very beginning of the SPL. The code consists
of some 32 instructions, uses APMU to configure CA76 start address to offset
0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The
code parts the CR52 core in an endless loop once the CA76 core got started.
The 32 instructions are completely arbitrary number, so is the offset 0x80
Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per
instruction is 32 instructions. The 32 instructions turned out to be enough
to started the CA76 and 0x80 is nicely aligned.
Once the SPL completes hardware initialization, the SPL loads U-Boot proper.
The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and
a DT for R8A779G0 V4H White Hawk board and is generated by binman. The
u-boot.itb is loaded from SPI NOR offset 0x80000.
In order to install this setup on an existing R8A779G0 V4H White Hawk board,
build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin
and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin
switches according to the R8A779G0 V4H White Hawk board documentation for
40 MHz SPI NOR boot using DMA and restart the board.
Signed-off-by: Marek Vasut <[email protected]>
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Make the R-Car V3U stub PSCI implementation available on 64bit R-Car SoCs.
This implementation is useful during early board bring up, where it can
supplant missing fully-featured PSCI implementation. Note that this PSCI
implementation is very basic and offers only SoC reset functionality. It
is unable to enable or disable secondary CPU cores nor does it offer any
suspend/resume functionality.
Signed-off-by: Marek Vasut <[email protected]>
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Describe DBSC5 DRAM controller and RT-VRAM configuration interface
as two new DT nodes in R-Car Gen4 R8A779G0 U-Boot DT extras file.
This node is used by the U-Boot SPL for R8A779G0 SoC, where the
DBSC5 and RT-VRAM drivers bind to these nodes and bring up the
DRAM controller and RT-VRAM settings respectively, so U-Boot
proper can be loaded into DRAM and started on Cortex A76 core.
Signed-off-by: Marek Vasut <[email protected]>
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Changes:
* update to new tcp stack
* fix zero values for ISS and IRS issue (see RFC 9293)
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The GW7905 was renamed to GW7500 before release. Change the various
names in the dt files and references.
Signed-off-by: Tim Harvey <[email protected]>
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Prepare v2025.01-rc5
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Drop global ddrphy_trained_csr which maybe different with per board
ddrphy_trained_csr. DDR TOOL generates ddrphy_trained_csr for each
board, using the global ddrphy_trained_csr has risk that values may
be not up to date.
Signed-off-by: Peng Fan <[email protected]>
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With an IMX8MP based SOM the SPI RST is gpio4_9 instead of gpio1_11.
Fix this.
Signed-off-by: Tim Harvey <[email protected]>
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commit e27bddff4b97 ("imx8m: Restrict usable memory to space below 4G boundary")
tried to adjust the usable memory limits on a 4GB boundary.
ram_top is described as 'top address of RAM used by U-Boot' and we want
to preserve that. This is defined as a phys_addr_t and unfortunately
its size differs across architectures. This has lead us to a weird
state where 32bit boards define it 'SZ_4GB - 1' and 64bit boards as
'SZ_4GB' unless it was otherwise defined.
With some recent LMB changes and specifically
commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank")
the board fails to boot properly although the commit above is correct
since it's making sure that no memory above ram_top is usable -- but
added to our memory map so EFI can hand it over to the booted OS.
The reason for that is that during the LMB init we add all usable memory
in lmb_add_memory(). In that function any memory above ram_top gets added
as 'reserved' for LMB. With the current values tha's set to 0xFFFF_FFFF
for this board. Later LMB is trying to protect the memory area U-Boot lives
in with lmb_reserve_common(). The latter fails though since it tries to
add U-Boot top (which is 0xFFFF_FFFF as well) to U-Boot 'bottom'. This call
will fail since 1 byte of that memory range is already marked as 'reserved'.
Since we are close to the release, LMB seems to assume that the address
is rounded up and is the 'next address' and so does parsing and adding
memory ranges from DT files, bump the ram_top of the board by 1byte.
In the long run we should change all of the above and have 32b and 64b
platforms define ram_top identically.
Add a Fixes tag although the commit is correct, so people can figure out
the broken scenarios in the future.
Suggested-by: Sughosh Ganu <[email protected]>
Fixes: commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank")
Signed-off-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Reported-by: João Paulo Gonçalves <[email protected]>
Closes: https://lore.kernel.org/all/[email protected]/
Reviewed-by: Peng Fan <[email protected]>
Fixes: 74f88b72219e ("ARM: imx: imx8m: Fix board_get_usable_ram_top()")
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Support of legacy 64-bit entry point was already present when booting a bzimage
with 'zboot' but not supported with 'bootm' when the x86_64 Linux kernel is
embedded in a FIT image.
Signed-off-by: Paul HENRYS <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This returns a devicetree and updates a parameter with an error code.
Swap it, since this fits better with the way U-Boot normally works. It
also (more easily) allows leaving the existing pointer unchanged.
No yaks were harmed in this change, but there is a very small code-size
reduction.
For sifive, the OF_BOARD option must be set for the function to be
called, so there is no point in checking it again. Also OF_SEPARATE is
defined always.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
[trini: Update total_compute]
Signed-off-by: Tom Rini <[email protected]>
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into next
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23926
- Board: Support LicheeRV Nano
- Board: Support bananapi-f3
- Board: Switch to OF_UPSTREAM for StarFive JH7110
- Board: Add sdhci driver for TH1520 SoC
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The root oscillators reference used to be in rcc node since
3d15245502c4 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver")
however this is not part of upstream stm32mp151.dtsi . The
RCC driver does need this reference, reinstate it locally.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The root oscillators reference used to be in rcc node since
3d15245502c4 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver")
however this is not part of upstream stm32mp151.dtsi . The
RCC driver does need this reference, reinstate it globally.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
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Add basic support for SpacemiT's Banana Pi F3 board.
Update the k1.dtsi align with mainline.
Note that the device tree files follow the mainline Linux source[1].
Links: https://patches.linaro.org/project/linux-serial/patch/[email protected]/ [1]
Signed-off-by: Kongyang Liu <[email protected]>
Signed-off-by: Huan Zhou <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yixun Lan <[email protected]>
Tested-by: Marcel Ziswiler <[email protected]>
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Add SDHCI and EMMC controlles nodes on TH-1520 SoC. And enable them for
Lichee module 4A.
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Maksim Kiselev <[email protected]>
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The imply statements should be sorted in the sequence
of appearance in .config.
Tested-by: Anand Moon <[email protected]>
Tested-by: E Shattow <[email protected]>
Suggested-by: Heinrich Schuchardt <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
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Support multiple DTBs for JH7110 based boards, so they can
select the correct DT at runtime.
Tested-by: Anand Moon <[email protected]>
Tested-by: E Shattow <[email protected]>
Reviewed-by: E Shattow <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
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To support the other JH7110 based boards, add u-boot
device tree for them.
Tested-by: Anand Moon <[email protected]>
Tested-by: E Shattow <[email protected]>
Reviewed-by: E Shattow <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>
Cc: H Bell <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
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To support JH7110 based boards besides v1.3B,
add a common dtsi and add common code to it.
Tested-by: Anand Moon <[email protected]>
Tested-by: E Shattow <[email protected]>
Reviewed-by: E Shattow <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
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Add u-boot features to the U-Boot device tree.
Tested-by: Anand Moon <[email protected]>
Tested-by: E Shattow <[email protected]>
Reviewed-by: E Shattow <[email protected]>
Acked-by: Sumit Garg <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
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Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to
the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi
to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b
device tree as the default device tree.
Drop redundant DT files from arch/riscv/dts/ and redundant clock and
reset definitions from include/dt-bindings/.
Since the old clock definitions is a little different from those in
upstream Linux, update the clock definitions in clock drivers
accordingly.
Tested-by: Anand Moon <[email protected]>
Tested-by: E Shattow <[email protected]>
Acked-by: Sumit Garg <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
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The LicheeRV Nano is a small SBC using the Sophgo SG2002 RISCV SoC.
Signed-off-by: Thomas Bonnefille <[email protected]>
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Import a slightly modified version of the LicheeRV Nano and SG2002
device trees from the Linux Kernel. The current supported IPs are UART,
MMC, Timer, PLIC and CLINT.
Signed-off-by: Thomas Bonnefille <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23877
- Add support for Apalis iMX8 1300MHz version.
- Don't advertise Gbit on (R)MII on the FEC controller.
- Fix srktool -c usage by removing spaces.
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Previously, all LMB marked with LMB_NOMAP (above and below ram_top)
are considered as invalid entry in TLB.
Since commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top
even from same bank") all LMB located above ram_top are now marked
LMB_NOOVERWRITE and no more LMB_MAP.
This area above ram_top is reserved for OPTEE and must not be cacheable,
otherwise this leads to a Panic on some boards (Issue on STM32MP135F-DK).
Restore previous behavior by marking invalid entry all TLB above ram_top.
Fixes: 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank")
Signed-off-by: Patrice Chotard <[email protected]>
cc: Sughosh Ganu <[email protected]>
Acked-by: Sughosh Ganu <[email protected]>
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Fix spelling mistake in the board init files of j721e and j721s2.
s/WKUP_DEVSTAT_MCU_OMLY_MASK/WKUP_DEVSTAT_MCU_ONLY_MASK
Signed-off-by: Prasanth Babu Mantena <[email protected]>
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Set correct CPU and GPU frequencies for the industrial i.MX8 SoC
variant.
Ensure that the CPU and GPU frequencies are properly configured for the
industrial variant of the SoC. According to the "i.MX 8QuadMax
Industrial Applications Processors" datasheet, the frequency limits for
this variant are as follows:
- Cortex-A72: 1.296 GHz
- Cortex-A53: 1.104 GHz
- GPU core: 625 MHz
- GPU shader: 625 MHz
The CPU clock is enforced by the System Controller Firmware (SCFW), but
the cpufreq driver is unaware of this enforcement. By removing
unsupported frequencies from the operating points, we ensure that the
cpufreq driver aligns correctly with the SCFW's settings.
The GPU frequency, on the other hand, is not enforced by the SCFW. As a
result, the GPU could potentially be overclocked. To prevent this, we
set the correct clock frequency and update the operating points
accordingly, ensuring compliance with the datasheet specifications.
Signed-off-by: Stefan Eichenberger <[email protected]>
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Since commit 61ff13283c3b ("board: sl28: move to OF_UPSTREAM") USB0 is
broken because the former u-boot soc dtsi was setting dr_mode to "host"
but the linux device tree isn't. That is because linux fully supports
OTG but u-boot doesn't. Therefore, u-boot only ever enabled host mode
and never OTG mode. Add it to our board "-u-boot.dtsi" to fix it.
Fixes: 61ff13283c3b ("board: sl28: move to OF_UPSTREAM")
Reported-by: Heiko Thiery <[email protected]>
Signed-off-by: Michael Walle <[email protected]>
Tested-by: Heiko Thiery <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Anurag Dutta <[email protected]> says:
Hi All,
In u-boot, hbmc is broken and has been removed from j7200
configs. This series re-enables the hbmc driver and introduces a series
of hyperflash boot fixes. At present, in u-boot, the parent device (fss)
gets registered as a syscon device. This is done because the MMIO
mux driver in u-boot did not support the mux functionality when the
parent device is not a syscon. In this series, we make relevant changes
in the hbmc driver as well as dts' so that we can use the reg-mux driver for
selecting the appropriate state of the mux.
Test logs:
1) j721e-idk-gw hyperflash boot test: https://gist.github.com/anuragdutta731/50aae6fec707a3ffad6d985de6757fe4
2) j7200-evm hyperflash boot test: https://gist.github.com/anuragdutta731/c3a4d60f8bfd9c425d6c44b36eb7322b
Link: https://lore.kernel.org/r/[email protected]
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Add 32-bit address overrides for Hyper Bus Memory Controller
for Hyperflash to be functional in R5 SPL.
Signed-off-by: Vaishnav Achath <[email protected]>
Signed-off-by: Anurag Dutta <[email protected]>
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Add 32-bit address overrides for Hyper Bus Memory Controller
for Hyperflash to be functional in R5 SPL.
Signed-off-by: Vaishnav Achath <[email protected]>
Signed-off-by: Anurag Dutta <[email protected]>
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Garrett Giordano <[email protected]> says:
This patch set adds the phyCORE AM62Ax board support and documenation to
u-boot.
The phyCORE-AM62Ax is a SoM (System on Module) featuring TI's AM62Ax SoC. It can
be used in combination with different carrier boards. This module can come
with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs
from the AM62x family.
A development Kit, called phyBOARD-Lyra is used as a carrier board reference
design around the AM62x SoM.
This series depends on the following two patches:
- [PATCH v2] arm: mach-k3: am62a7: Provide a way to obtain boot device for non SPL
https://lists.denx.de/pipermail/u-boot/2024-October/570156.html
- [PATCH] board: phytec: common: Introduce CONFIG_PHYTEC_K3_DDR_PATCH
https://lists.denx.de/pipermail/u-boot/2024-November/571543.html
Link: https://lore.kernel.org/r/[email protected]
[trini: Fix warning in board/phytec/common/k3/board.c when
CONFIG_EFI_HAVE_CAPSULE_SUPPORT is not enabled]
Signed-off-by: Tom Rini <[email protected]>
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Introduce get_boot_device() to obtain the booting device. Make it also
available for non SPL builds so u-boot can also know the device it
is booting from.
Signed-off-by: Garrett Giordano <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
Reviewed-by: Andrew Davis <[email protected]>
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Add support for PHYTEC phyCORE-AM62A7 SoM.
Supported features:
- 2GB LPDDR4 RAM
- eMMC
- External SD
- Ethernet
- debug UART
Signed-off-by: Garrett Giordano <[email protected]>
Reviewed-by: Wadim Egorov <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
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Wadim Egorov <[email protected]> says:
This implements capsule updates for all our K3 SoMs for
eMMC, OSPI NOR and uSD cards.
We can use capsule updates to update the bootloader on all our
supported flash devices.
Link: https://lore.kernel.org/r/[email protected]
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Fill in phycore-am64x capsule GUID properties of the base
binman capsule nodes.
Signed-off-by: Wadim Egorov <[email protected]>
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Fill in phycore-am62x capsule GUID properties of the base
binman capsule nodes.
Signed-off-by: Wadim Egorov <[email protected]>
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Udit Kumar <[email protected]> says:
This enables the ESMs and the associated PMIC. Programming these bits is
a requirement to make the watchdog actually reset the board.
Logs
WDT reset J721S2
https://gist.github.com/uditkumarti/93cfe863d1f3fe3abb82b1821105f274#file-j721s2-L2708
AM68 boot (this does not support WDT)
https://gist.github.com/uditkumarti/93cfe863d1f3fe3abb82b1821105f274#file-am68
Link: https://lore.kernel.org/r/[email protected]
[trini: Merge configs/am68_sk_r5_defconfig]
Signed-off-by: Tom Rini <[email protected]>
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