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ARMv7-M architecture uses NVIC instead of GIC.
NVIC is an interrupt controller specially designed for
ARM Cortex-M series processors.
Signed-off-by: Liya Huang <[email protected]>
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U-Boot can run out of EL3, NS-EL2 and NS-EL1. Currently default
configuration is NS-EL2 with TF-A but when TF-A is not passed and
configured images can still boot just fine. That's why support this
configuration and describe it via binman.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/9b3dad80138e97005df3d033b4611c9d7e05a177.1738659214.git.michal.simek@amd.com
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CONFIG_XILINX_OF_BOARD_DTB_ADDR holds DTB address which U-Boot is checking.
Currently address in binman match default value but macro can be used
directly.
Also sync node name (s/hash-1/hash/) and sync location to have the same
order load/hash/image.
All binman DTSes are compiled that's why also guard
CONFIG_XILINX_OF_BOARD_DTB_ADDR which depends on OF_BOARD || OF_SEPARATE
which is a problem for mini configurations which are using OF_EMBED.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/a22c9671b965b222bfd419f5bfaee012929f3d88.1738659214.git.michal.simek@amd.com
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There is incorrect loading address listed for TEE.
CONFIG_BL32_LOAD_ADDR should be used.
Also there is missing hash for this entry which is present for other nodes.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/4e7e3a7110acc050ea7c06ac661e5b5be46e8602.1738659214.git.michal.simek@amd.com
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Add ethernet aliases to CC (Carrier card) description to create a
connection which is used by fdt_fixup_ethernet() for updating
local-mac-address in DT.
On Kria SOM MAC address is read from i2c eeprom at start and based on it
environment variables are created. Without creating aliases U-Boot is not
able to inject local-mac-address DT property and OS won't get the same MAC
address unless another i2c read is happening in OS.
Also aliases are using string not phandle that's why full path has to be
provided but that shouldn't be a big issue because location of ethernet
controller is fixed.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/6d360e71a0530d201578e27a6997dbd472772e39.1737466907.git.michal.simek@amd.com
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Output images are generated via Binman only if SPL is enabled, as
there is no consumer for them otherwise. An #ifdef check ensures that
when SPL is enabled, Binman generates the U-Boot ITB. If SPL is disabled,
ITB generation is skipped since the ITB format is supported only by SPL.
Without SPL, generating such an image is unnecessary, as it would not be
used
The second reason is that when a DTB is passed, the current logic cannot
handle it without an additional step in U-Boot to parse an appended FIT
image and enable board-specific code to select the correct DTB config.
The MULTI_DTB_FIT configuration should be used if support for multiple
DTBs is required, but SPL is not being used.
Signed-off-by: Prasad Kummari <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/7cba738ae36dacf7d1b0cfbaf13e0c9b3a0df225.1737462296.git.michal.simek@amd.com
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The commit e05689242238 ("Kconfig: Change SYS_MALLOC_F_LEN default to
0x2000") already setup default values from board Kconfigs that's why no
reason to duplicate it again.
Fixes: e05689242238 ("Kconfig: Change SYS_MALLOC_F_LEN default to 0x2000")
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/c3edd75b7a19d5cc205c9d5c37c2d86189ca3de6.1737380025.git.michal.simek@amd.com
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Add support for the R-Car S4 Starter Kit with R8A779F4 SoC support.
This implementation natively uses OF_UPSTREAM to pull in most recent
DT. The defconfig is derived from S4 Spider, with reduced UART baud
rate to 921600 Bdps. The DT alias to rswitch is removed as the alias
should point to rswitch ports, not to rswitch itself, see [1].
[1] https://lore.kernel.org/linux-arm-kernel/[email protected]/
Signed-off-by: Marek Vasut <[email protected]>
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Explicitly flush icache on the CR52 core before jumping to the next
stage software to make sure it does not contain any invalid content.
Explicitly flash and invalidate dcache on the CA76 core both over the
trampoline buffer and over the CR52 firmware, and then trigger full
system synchronization, to make sure the data surely land in DRAM,
from where the CR52 can surely pick them up.
Signed-off-by: Marek Vasut <[email protected]>
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Christian Marangi <[email protected]> says:
This is the last batch of part to push actual support of
OF_UPSTREAM for the mediatek SoC.
The plan is to make the current downstream DTS on part with
upstream implementation so we can permit a gradual transition to
it while we don't cause any regression to any user.
This is to have the same node downstream and upstream.
Mediatek is working hard upstream to also push all the remaining
nodes.
All patch are the final changes after the pinctrl patch
merged previously.
All patch pass CI tests
Link: https://github.com/u-boot/u-boot/pull/731
Link: https://lore.kernel.org/r/[email protected]
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Add PCIe node for MT7981 with all the required properties to make PCIe
work.
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Weijie Gao <[email protected]>
Tested-by: Weijie Gao <[email protected]>
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Add USB PHY nodes for MT7981. These are needed for USB support and also
for PCIe support as the u3 PHY can also be used for PHY.
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Weijie Gao <[email protected]>
Tested-by: Weijie Gao <[email protected]>
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Move gpio-controller up to pinctrl node and rename label to "pio" to
match the label used in upstream kernel linux.
Update any DTS that reference the pinctrl to follow the new naming and
structure.
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Weijie Gao <[email protected]>
Tested-by: Weijie Gao <[email protected]>
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Move gpio-controller up to pinctrl node and rename label to "pio" to
match the label used in upstream kernel linux.
Update any DTS that reference the pinctrl to follow the new naming and
structure.
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Weijie Gao <[email protected]>
Tested-by: Weijie Gao <[email protected]>
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Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Weijie Gao <[email protected]>
Tested-by: Weijie Gao <[email protected]>
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Move gpio-controller up to pinctrl node and rename label to "pio" to
match the label used in upstream kernel linux.
Update any DTS that reference the pinctrl to follow the new naming and
structure.
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Weijie Gao <[email protected]>
Tested-by: Weijie Gao <[email protected]>
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Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Weijie Gao <[email protected]>
Tested-by: Weijie Gao <[email protected]>
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Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Weijie Gao <[email protected]>
Tested-by: Weijie Gao <[email protected]>
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JH7110 SoC requires no specific handling before entering Linux kernel.
Let's drop the specific implementation to avoid duplication.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The current implementation is equivalent to the fallback one, so
this shouldn't change any behaviour but cleans the code up only.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Most RISC-V SoCs have similar cleanup_before_linux() functions. Let's
provide a weak symbol as fallback to reduce duplicated code.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The following diagram illustrates the boot flow for OP-TEE OS
initialization on RISC-V.
(1)-----------+
| U-Boot SPL |
+------------+
|
v
(2)-------------------------------------------------------------+
| OpenSBI (fw_dynamic.bin) |
| (4)------------------------+ |
| | optee dispatcher driver | |
+-----------------+-------^---------|-------+------------------+
M-mode | | |
---------+--[trusted domain]---+----.----+--[untrusted domain]-------
S-mode | (coldboot domain) | | |
v | | v
(3)---------------------------+ |(5)----------------------------+
| OP-TEE OS (tee.bin) | | | U-Boot (u-boot-nodtb.bin) |
+----------------------------+ | +-----------------------------+
| |
| v
|(6)----------------------------+
| | Linux |
| +-----------------------------+
This patch enables the inclusion of the OP-TEE binary within the
U-Boot ITB, allowing it to be loaded to a platform defined address
by U-Boot SPL.
Signed-off-by: Yu-Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Allow specifying load address of OP-TEE binary. It is
recommended that the specified address aligns with the
base address of an PMP-protected NAPOT region and matches
the CFG_TDDRAM_START configuration in OP-TEE.
Signed-off-by: Yu-Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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If CONFIG_AVAILABLE_HARTS=y, variable available_harts_lock is created in
the data section which will not be writable while executing from flash.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Implement functionality to probe and calculate the DRAM size
during the boot phase for the RISC-V spacemit K1 platform.
Tested-by: Marcel Ziswiler <[email protected]> # BPI-F3 16G
Signed-off-by: Huan Zhou <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-stm
STM32 MPU:
- Remove dt-bindings headers available in dts/upstream
- Fixes for stm32prog
- Enable CONFIG_SYS_64BIT_LBA for STM32MP15/13/25 defconfigs
- Add upport of ck_usbo_48m in pre-reloc stage for STM32MP13
- Clean env_get_location() for STM32MP1
- Fix board_get_usable_ram_top() to fix infinite loop in cache
management for STM32MP2.
- Fix ck_flexgen_08 frequency for STM32MP2
STM32 MCU:
- Tune CYCLIC_MAX_CPU_TIME_US to avoid cyclic warning for STM32F469-Disco
- Tune CYCLIC_MAX_CPU_TIME_US to avoid cyclic warning for STM32F769-Disco
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Spurious characters are displayed on U-Boot console.
Usart2 clock is ck_flexgen_08 and its frequency is set
to an incorrect value.
Update ck_flexgen_08 frequency from 100MHz to 64MHz.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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mmu_set_region_dcache_behaviour() parameters must be aligned
which is not always the case.
For example for STM32MP2, we stayed stuck inside
mmu_set_region_dcache_behaviour() in an infinite loop because
set_one_region() always return 0 due to start parameter which is
not aligned.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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The clock ck_usbo_48m is a clock source for RCC, so the ck_usbo_48m
clock provided by usbphyc need to be probed when RCC clock driver is
required, in pre-reloc stage.
This patch allow to remove the following warning:
clk_register: failed to get ck_usbo_48m device (parent of usbo_k)
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Set multiplier to 'G' if part->size if above SZ_1G.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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If CONFIG_SYS_64BIT_LBA flag is enable, following warning is triggered:
../arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c: In function 'init_device':
../arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c:793:27: warning: format
'%ld' expects argument of type 'long int', but argument 8 has type
'lbaint_t' {aka 'long long unsigned int'} [-Wformat=]
793 | log_debug("MMC %d: lba=%ld blksz=%ld\n", dev->dev_id,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../include/log.h:157:21: note: in definition of macro 'pr_fmt'
157 | #define pr_fmt(fmt) fmt
| ^~~
../include/log.h:182:33: note: in expansion of macro 'log'
182 | #define log_debug(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG, ##_fmt)
| ^~~
../arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c:793:17: note: in expansion
of macro 'log_debug'
793 | log_debug("MMC %d: lba=%ld blksz=%ld\n", dev->dev_id,
| ^~~~~~~~~
../arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c:793:42: note: format string
is defined here
793 | log_debug("MMC %d: lba=%ld blksz=%ld\n", dev->dev_id,
| ~~^
| |
| long int
| %lld
Cast block_dev->lba to u64 and set the length specifier to %lld which
is ok with or without CONFIG_SYS_64BIT_LBA flag.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Weijie Gao <[email protected]> says:
This patch series add support for MediaTek MT7987 SoC with its reference
boards and related drivers.
This patch series add basic boot support on eMMC/SD/SPI-NOR/SPI-NAND for these
boards. The clock, pinctrl drivers and the SoC initializaton code are also
included.
Link: https://lore.kernel.org/r/[email protected]
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This patch adds general board files based on MT7987 SoC.
MT7987 uses one mmc controller for booting from both SD and eMMC, and the
pins of mmc controller are also shared with one spi controller.
So three configs are need for these boot types:
1. mt7987_rfb_defconfig - SPI-NOR (spi2) and SPI-NAND (spi0)
2. mt7987_emmc_rfb_defconfig - eMMC + SPI-NOR (spi2)
3. mt7987_sd_rfb_defconfig - SD + SPI-NOR (spi2)
Note: spi2 also supports booting from SPI-NAND, but not the default option.
Signed-off-by: Sam Shih <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds basic support for MediaTek MT7987 SoC.
This includes files that will initialize the SoC after boot and
its device tree.
In order to maximize the continuous usable memory space, MT7987 has its
ATF BL31 loaded at the top of RAM. Since u-boot will also locate itself to
top of RAM, u-boot will read the actual memory region of BL31 and set
correct gd->ram_top to avoid u-boot overlapping with BL31.
As now support for mt7987 hasn't been submitted to linux kernel, all dts
filed will be put to arch/arm/dts. They'll be removed after successfully
being merged by linux kernel, and OF_UPSTREAM will also be switched on.
Signed-off-by: Weijie Gao <[email protected]>
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Samsung Galaxy Core Prime VE LTE is an entry-level PXA1908-based
smartphone. It has 1GB of DRAM, 8GB eMMC and USB connectivity.
Signed-off-by: Duje Mihanović <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Add initial support for Marvell PXA1908. The SoC has 4 Cortex-A53 cores,
a GC7000UL GPU and a variety of peripheral controllers.
Signed-off-by: Duje Mihanović <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Enable bootstd for OpenRD boards
Update defconfigs to the latest u-boot requirements
Remove JFFS2 support. See JFFS2 Vulnerability[1].
Move default envs to text-base environment
[1] https://lore.kernel.org/u-boot/20241114233005.GN3600562@bill-the-cat/T/#m2fc25da1d2c019bc3cd8676991fdd64b8a21aa9b
Signed-off-by: Tony Dinh <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/24366
- Refactor the imx pinctrl driver.
- Enable optional ENETREF clock on i.MX95
- Remove optional from tee-os entry on the i.MX8M u-boot devicetrees.
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
[rockchip fixes from Jonas Karlman via IRC]
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tee-os node is guarded by CONFIG_OPTEE. Since OPTEE adds driver support
for OP-TEE, the binary should then be packaged in the bootable image.
Remove the optional property to enforce this requirement.
Signed-off-by: Yannic Moog <[email protected]>
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Simon Glass <[email protected]> says:
The current method of running unit tests relies on subcommands of the
ut command. Only the code in each subcommand knows how to find the tests
related to that subcomand.
This is not ideal and we now have quite a few subcommands which do
nothing but locate the relevant tests in a linker list, then call a
common function to run them.
This series adds a list of test suites, so that these subcommands can be
removed.
An issue with 'ut all' is that it doesn't record how many tests failed
overall, so it is necessary to examine copious amounts of output to look
for failures. This series adds a new 'total' feature allow recording the
total number of failed tests.
To help with 'ut all' a new pytest is created which runs it (as well as
'ut info') and makes sure that all is well. Due to the 'ut all' failures
this does not pass, so the test is disabled for now. It is here because
it provides security against misnaming a test suite and causing it not
to run.
Future work may:
- get 'ut all' passing
- enable test_suite() in CL, to ensure that 'ut all' keeps passing
- record duration of each suite
- allow running the tests in random order to tease out dependencies
- tweak the output to remove common prefixes
- getting rid of bootstd, optee and seame 'ut' subcommands
Link: https://lore.kernel.org/r/[email protected]
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Add a function to show the stats, so we can decide when to print it.
This slightly adjusts the output, so that any 'test not found' message
appears on its own line after all other output.
The 'failures' message now appears in lower case so update pytest
accordingly.
Signed-off-by: Simon Glass <[email protected]>
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Pass this into the function so that callers can inspect the state
afterwards.
Signed-off-by: Simon Glass <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga
1. Bug fixed for doorbell in secure device manager mailbox driver
2. Enhancement on SoCFPGA dwc_eth_xgmac driver
3. Enhancement on DW MAC driver
4. Improved the error message and status for SoC64 device FPGA
configuration driver
5. Updated existing watchdog in system manager to support new SM device
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Currently the FPGA reconfig status only return a single error status
which make the debugging of FPGA reconfiguration hard.
This patch is to expose the error status, major error code and
minor error code, for the FPGA reconfig to upper layer app.
Signed-off-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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The current write and notify SDM to read mechanism has a flaw where
SDM is not notified enough to be able to read all the data in the buffer.
This is caused by SDM doorbell will only be sent out once the command
buffer overflow check is satisfied. If the command buffer does not reach
overflow status, no SDM doorbell will be sent out, which may cause a
timeout as the mailbox driver will be waiting for the SDM to read the
buffer to empty even though SDM is not notified to do so.
The solution is to remove the command buffer overflow check
and set the SDM doorbell to always trigger at the end of the command
buffer.
This will ensure that the SDM is able to read all of the data.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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This commit is to fix the system manager watchdog mode setting to support
until mode_4 for Agilex5. This changes can refer to system manager register
map on wddbg fields.
In Agilex7 it is not detected as an issue because Agilex7 only have 4 watchdog
until mode_3 and it is already been set correctly for it to halt on any CPU in
debug mode. However, in Agilex5 this fix is needed in order to enable the watchdog
pause feature for mode_4 when entering debug mode. If 0xF is not been set on mode_4,
the Watchdog Timers will not halt on any CPU. As by default value, the pause signal
does not assert when any CPU is in debug mode and the watchdog continue to count.
Signed-off-by: Muhammad Hazim Izzat Zamri <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Michael Chang <[email protected]> says:
I am resubmitting the patch titled "Add bitbang feature for npcm8xx
and driver" for review and inclusion in the upstream project.
Driver didn't support bitbang feature.
Add bb_miiphy_bus function for driver and open feature for npcm8xx
the log is as below:
-------------------------------------------------
U-Boot 2024.10-g30b9cdaf2df5-dirty (Jan 09 2025 - 00:57:37 +0000)
CPU-0: NPCM845 A1 @ Model: Nuvoton npcm845 Development Board (Device Tree)
DRAM: 1 GiB
RNG: NPCM RNG module bind OK
OTP: NPCM OTP module bind OK
AES: NPCM AES module bind OK
SHA: NPCM SHA module bind OK
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
Core: 649 devices, 28 uclasses, devicetree: separate
WDT: Not starting watchdog@901c
MMC: sdhci@f0842000: 0
Loading Environment from SPIFlash... SF:
Detected w25q512jvq with page size 256 Bytes, erase size 64 KiB,
total 64 MiB
OK
In: serial@0
Out: serial@0
Err: serial@0
Net: eth0: eth@f0802000, eth1: eth@f0804000, eth3: eth@f0808000
Hit any key to stop autoboot: 0
U-Boot>
U-Boot>
U-Boot>setenv ipaddr 192.168.16.3
U-Boot>ping 192.168.16.12
eth@f0802000 Waiting for PHY auto negotiation to complete
......... TIMEOUT !
Could not initialize PHY eth@f0802000
eth@f0804000 Waiting for PHY auto negotiation to complete
......... TIMEOUT !
Could not initialize PHY eth@f0804000
Speed: 100, full duplex
Using eth@f0808000 device
host 192.168.16.12 is alive
Link: https://lore.kernel.org/r/[email protected]
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Add bitbang delay through dts properties.
Signed-off-by: Jim Liu <[email protected]>
Signed-off-by: Michael Chang <[email protected]>
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Weijie Gao <[email protected]> says:
This patch series contains fixes and updates for MediaTek platform,
including drivers, board and arch files.
Link: https://lore.kernel.org/r/[email protected]
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