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Put the pointer to this structure in struct vidinfo so that we can
reference it without it being global.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Use 'struct vidinfo' instead so that we can change this to a struct with a
different name in future.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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We always use device tree with video, so can drop these #ifdefs. Some of the
hardware addresses are not needed either.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Espresso7420 is a development/evaluation board for Exynos7420 SoC. It
includes multiple onboard compoments (EMMC/Codec) and various
interconnects (USB/HDMI).
Signed-off-by: Thomas Abraham <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Add support for Exynos7420 SoC. The Exynos7420 SoC has four Cortex-A57
and four Cortex-A53 CPUs and includes various peripheral controllers.
Signed-off-by: Thomas Abraham <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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The existing Exynos 32-bit platform support needs to be realigned in
order to support newer 64-bit Exynos platforms. The driver model will
be utlized for drivers on the 64-bit Exynos platforms and so some of
the older platform support code would not be required for the newer
64-bit Exynos platforms.
Cc: Minkyu Kang <[email protected]>
Signed-off-by: Thomas Abraham <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
drivers/net/zynq_gem.c
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Fix typo error for cpsw device name with proper device address
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add syscon node to cpsw device node to read mac address
from efuse.
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add syscon node to cpsw device node to read mac address
from efuse.
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add platforms specific phy mode configuration bits to be used
to configure phy mode in control module.
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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To i.MX6DQPlus, osc can be choosed as the source of gpt, so
add i.MX6DQPlus support in gpt_has_clk_source_osc.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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The i.MX6DQPlus support sata interface, we should not
return failure when CPU is i.MX6DQPlus.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Support i.MX6DQPlus, otherwise wrong hab address will be used
for i.MX6QDPlus.
Signed-off-by: Peng Fan <[email protected]>
Cc: Ulises Cardenas <[email protected]>
Cc: Stefano Babic <[email protected]>
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Correct get_cpu_speed_grade_hz for i.MX6DQP, otherwise we
will get wrong speed grade info i.MX6DQP.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Support i.MX6D/QPlus.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Use simpler runtime cpu dection macros.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Bhuvanchandra DV <[email protected]>
Cc: "Benoît Thébaudeau" <[email protected]>
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Add i.MX6SOLO support for hab function.
The difference between i.MX6SOLO and i.MX6DL is
the number of CPU cores. Besides this, they work
the same.
Signed-off-by: Peng Fan <[email protected]>
Cc: Bhuvanchandra DV <[email protected]>
Cc: "Benoît Thébaudeau" <[email protected]>
Cc: Stefano Babic <[email protected]>
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Use simpler runtime cpu dection macros.
i.MX6DL and i.MX6SOLO work the same, so use is_mx6sdl.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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i.MX6DL and i.MX6SOLO work the same, add i.MX6SOLO support
when enable/disable_ldb_di_clock_sources.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Introduce simpler macros for runtime cpu dection.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Extending Kconfig for adding new platform is a lot of work
for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and
remove all dependencies on TARGET_ZYNQ_* options including SPL.
As a side-effect it also remove custom init folder for ps7_init_gpl.*
files. Folder is chosen based on device-tree file.
Signed-off-by: Michal Simek <[email protected]>
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Support RAM and MMC boot mode in SPL also with SPL_FIT images.
In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
-d bl31.bin atf.ub
cp spl/boot.bin <sdcard fat partition>
cp atf.ub <sdcard fat partition>
cp u-boot.bin <sdcard fat partition>
2) Boot flow with full U-Boot(EL3):
cp spl/boot.bin <sdcard>
cp u-boot*.img <sdcard>
3) emmc boot mode
dd if=/dev/zero of=sd.img bs=1024 count=1024
parted sd.img mktable msdos
parted sd.img mkpart p fat32 0% 100%
kpartx -a sd.img
mkfs.vfat /dev/mapper/loop0p1
mount /dev/mapper/loop0p1 /mnt/
cp spl/boot.bin /mnt
cp u-boot.img /mnt
cp u-boot.bin /mnt
cp atf.ub /mnt
umount /dev/mapper/loop0p1
kpartx -d sd.img
cp sd.img /tftpboot/
and program it via u-boot
tftpb 10000 sd.img
mmcinfo
mmc write 10000 0 $filesize
mmc rescan
mmc part
ls mmc 0
psu_init() function contains low level SoC setup generated for every HW
design by Xilinx design tools. xil_io.h is only supporting file to fix
all dependencies from tools. The same solution was used on Xilinx Zynq.
The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which
stays at the same location all the time.
Bootrom expects starting address to be at 0xfffc0000 that's why this
address is SPL_TEXT_BASE.
Signed-off-by: Michal Simek <[email protected]>
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Add missing u-boot,dm-pre-reloc to get IPs initialized.
Signed-off-by: Michal Simek <[email protected]>
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The GIC ranges in the zynqmp device tree are only 4kb aligned. Since
commit 12e14066f we automatically deal with aliases GIC regions though,
so we can map them transparently into guests even on 64kb page size
systems.
This patch makes use of that features and sets GICC and GICV to 64kb
aligned and sized regions.
Signed-off-by: Alexander Graf <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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If ps7_post_config() is defined call it. It is enabling for example
level shifters for PL bitstreams.
Signed-off-by: Michal Simek <[email protected]>
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Enable minimal function to be able to compile SPL_LOAD_FIT.
Signed-off-by: Michal Simek <[email protected]>
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Commit 9f56917ab88a ("dm: core: make simple-bus compatible to
simple-mfd") made possible to import the following commit:
Linux commit: bc5ba9b98435bf76d92e0954da1784695aa449f1
The SLCR (System-Level Control Registers) block is an MFD (Multi
Function Device) rather than a bus.
"simple-mfd" seems a more suitable compatible string than "simple-bus".
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Implement support for saving ARM register R4 early during boot using
save_boot_params . Implement support for decoding the stored register
R4 value in spl_boot_device() to obtain boot device from which the
SoC booted. This way, the SPL will always load U-Boot from the same
device from which the SPL itself booted instead of using hard-coded
boot device.
This functionality is useful for example when booting sama5d2-xplained
from SD card, where by default the SPL would try loading the U-Boot
from eMMC and fail. This is because eMMC is on SDHCI0 (BOOT_DEVICE_MMC1),
while SD slot is on SDHCI1 (BOOT_DEVICE_MMC2) and the SPL was hard-wired
to always boot from BOOT_DEVICE_MMC1.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Andreas Bießmann <[email protected]>
Cc: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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Add the UPLL clock and master clock as a clock source for getting
the generated clock frequency to complete its clock sources support.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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Before enabling a generated clock whose source is from the UPLL
clock, check and enable the UPLL clock.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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The board supports following features:
- Boot media support: NAND Flash/SPI Flash
- Support ethernet
- Support USB mass storage
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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They will be used on SAMA5D2 PTC board.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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Commit 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()")
accidentally inverted the logic of CONFIG_ARMV8_MULTIENTRY.
Fixes: 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()")
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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Make use of the newly added Kconfig options of board manufacturer
and product name to write SMBIOS tables.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This introduces two Kconfig options to be used by SMBIOS tables:
board manufacturer and product name.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Currently ID 2 is assgined to broadwell I/O APIC, however per
chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change
I/O APIC ID to 4 to avoid conflict.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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After power-on, both LAPIC and I/O APIC appear with the same APIC ID
zero, which creates an ID conflict. When generating MP table, U-Boot
reports zero as the LAPIC ID in the processor entry, and zero as the
I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment
entries. Such MP table confuses Linux kernel and finally a kernel
panic is seen during boot:
BUG: unable to handle kernel paging request at ffff9000
IP: [<c101d462>] native_io_apic_write+0x22/0x30
*pdpt = 00000000014fb001 *pde = 00000000014ff067 *pte = 0000000000000000
Oops: 0002 [#1]
Modules linked in:
Pid: 1, comm: swapper Tainted: G W 3.8.7 #3 intel galileo/galileo
EIP: 0060:[<c101d462>] EFLAGS: 00010086 CPU: 0
EIP is at native_io_apic_write+0x22/0x30
...
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Let's configure LAPIC in a common place - interrupt_init().
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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At present LAPIC is enabled and configured as virtual wire mode
in lapic_setup() only when CONFIG_SMP is on. This limitation is
however not necessary as for uniprocessor this is still needed.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Intel Quark processor core provides an integrated Local APIC but
does not support the IA32_APIC_BASE MSR. As a result, the Local
APIC is always globally enabled and the Local APIC base address
is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE
MSR causes a general protection fault.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add a cpu node in the device tree and enable CPU driver.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update board device tree to include latest microcode, and remove
the old no longer needed microcode.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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