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We can simply use the default DT, Basic PG1, because no nodes that are
different between the variants play a role for SPL. Will help with the
migration to OF_UPSTREAM.
Signed-off-by: Jan Kiszka <[email protected]>
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Define CBO inval and flush instructions and use those for the
dcache inval and flush operations respectively.
Signed-off-by: Mayuresh Chitale <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add insn-def.h which is similar to that in linux and contains the macros
to generate any instruction of type 'I' using the assembler's .insn
directive.
Signed-off-by: Mayuresh Chitale <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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* Messages written with log_err() should be terminated with linefeed.
* Spell device-tree with hyphen as elsewhere in U-Boot.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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This patch series enables full RVVM virtual machine support which was
earlier inconveniently provided as out-of-tree patchset.
This should be cleaner than a separate board config, since both
emulators provide similar feature set.
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The SBI 3.0 specification [1] adds the following extensions:
* Firmware Features Extension
* Message Proxy Extension
Let the sbi command detect their availability.
The Firmware Features Extension is already implemented in OpenSBI.
Correct the text for the DBTR extension and move it to the same position
as in the specification.
[1] https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/vv3.0-rc1/riscv-sbi.pdf
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The config setting CMD_BOOTEFI_HELLO_COMPILE was removed in favour
of BOOTEFI_HELLO_COMPILE but the usage in this Makefile was not
updated. Fix it.
Fixes: 6fe80876dcc7 ("efi_loader: Rename and move CMD_BOOTEFI_HELLO_COMPILE")
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Patrick Rudolph <[email protected]> says:
Based on the existing work done by Simon Glass this series adds
support for booting aarch64 devices using ACPI only.
As first target QEMU SBSA support is added, which relies on ACPI
only to boot an OS. As secondary target the Raspberry Pi4 was used,
which is broadly available and allows easy testing of the proposed
solution.
The series is split into ACPI cleanups and code movements, adding
Arm specific ACPI tables and finally SoC and mainboard related
changes to boot a Linux on the QEMU SBSA and RPi4. Currently only the
mandatory ACPI tables are supported, allowing to boot into Linux
without errors.
The QEMU SBSA support is feature complete and provides the same
functionality as the EDK2 implementation.
The changes were tested on real hardware as well on QEMU v9.0:
qemu-system-aarch64 -machine sbsa-ref -nographic -cpu cortex-a57 \
-pflash secure-world.rom \
-pflash unsecure-world.rom
qemu-system-aarch64 -machine raspi4b -kernel u-boot.bin -cpu cortex-a72 \
-smp 4 -m 2G -drive file=raspbian.img,format=raw,index=0 \
-dtb bcm2711-rpi-4-b.dtb -nographic
Tested against FWTS V24.03.00.
Known issues:
- The QEMU rpi4 support is currently limited as it doesn't emulate PCI,
USB or ethernet devices!
- The SMP bringup doesn't work on RPi4, but works in QEMU (Possibly
cache related).
- PCI on RPI4 isn't working on real hardware since the pcie_brcmstb
Linux kernel module doesn't support ACPI yet.
Link: https://lore.kernel.org/r/[email protected]
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On FDT platforms the APs are brought out of reset using the spin-table
as defined in the DT. On ACPI enabled platforms there's no FDT, thus
enable the ARMV8_MULTIENTRY and BLOBLIST to use the ACPI parking
protocol instead.
TEST: - APs enter Linux when run on qemu-system-aarch64 -machine raspi4b
- APs on real hardware do not enter Linux, but continue spinning in
their ACPI parking protocol spinloop. To be investigated.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Matthias Brugger <[email protected]>
Cc: Peter Robinson <[email protected]>
Cc: Tom Rini <[email protected]>
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When ACPI is enabled over FDT the APs cannot be brought out of reset
by the OS using the "FDT spin-table" mechanism, as no FDT is provided
to the OS. The APs must be released out of reset in u-boot and then
brought up in an ACPI compliant fashion.
When ARMV8_MULTIENTRY is specified, the APs are released from reset
and will enter U-Boot after it has been relocated as well.
By default ARMV8_MULTIENTRY is not selected, keeping existing behaviour.
TEST: All APs enter U-Boot when run on qemu-system-aarch64 and on
real hardware.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Matthias Brugger <[email protected]>
Cc: Peter Robinson <[email protected]>
Cc: Tom Rini <[email protected]>
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Implement read_mpidr() on armv7 to make use of it in generic
code that compiles on both armv7 and armv8.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update the generic entry point code to support the ACPI parking protocol.
The ACPI parking protocol can be used when PSCI is not available to bring
up secondary CPU cores.
When enabled secondary CPUs will enter U-Boot proper and spin in their own
4KiB reserved memory page, which also acts as mailbox with the OS to
release the CPU.
TEST: Boots all CPUs on qemu-system-aarch64 -machine raspi4b
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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On Arm platforms that use ACPI they cannot rely on the "spin-table"
CPU bringup usually defined in the FDT. Thus implement the
'ACPI Multi-processor Startup for ARM Platforms', also referred to as
'ACPI parking protocol'.
The ACPI parking protocol works similar to the spin-table mechanism, but
the specification also covers lots of shortcomings of the spin-table
implementations.
Every CPU defined in the ACPI MADT table has it's own 4K page where the
spinloop code and the OS mailbox resides. When selected the U-Boot board
code must make sure that the secondary CPUs enter u-boot after relocation
as well, so that they can enter the spinloop code residing in the ACPI
parking protocol pages.
The OS will then write to the mailbox and generate an IPI to release the
CPUs from the spinloop code.
For now it's only implemented on ARMv8, but can easily be extended to
other platforms, like ARMv7.
TEST: Boots all CPUs on qemu-system-aarch64 -machine raspi4b
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Tom Rini <[email protected]>
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Generate SoC specific ACPI tables for BCM2711:
- FADT
- PPTT
- GTDT
Board specific tables like DSDT and SSDT are added in a separate patch.
MADT is already properly generated from the FDT.
When ACPI is enabled for a different SoC compliation will fail by
design, indicating the required functions that needs to be implemented.
When ACPI is not enabled the added code does nothing, keeping existing
behaviour.
TEST: Booted on RPi4 with only ACPI enabled, providing no FDT to the OS.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Matthias Brugger <[email protected]>
Cc: Peter Robinson <[email protected]>
Cc: Tom Rini <[email protected]>
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These header files presumably duplicate things already in the U-Boot
devicetree. For now, bring them in to get the ASL code and ACPI table
code to compile.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Matthias Brugger <[email protected]>
Cc: Matthias Brugger <[email protected]>
Cc: Peter Robinson <[email protected]>
Cc: Tom Rini <[email protected]>
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Cover the "ARM local MMIO" range as well in the default MMU mapping in
order to allow future code to access the GIC-400 without crashing. For
now the GIC is not touched in u-boot, thus this change is a noop.
See [1](BCM2711 ARM Peripherals) for reference.
TEST: Enabled CONFIG_GICV2 and accessed the GIC in C code without crash.
1: https://datasheets.raspberrypi.com/bcm2711/bcm2711-peripherals.pdf
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Matthias Brugger <[email protected]>
Cc: Matthias Brugger <[email protected]>
Cc: Peter Robinson <[email protected]>
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Add support for Arm sbsa [1] v0.3+ that is supported by QEMU [2].
Unlike other Arm based platforms the machine only provides a minimal
FDT that contains number of CPUs, ammount of memory and machine-version.
The boot firmware has to provide ACPI tables to the OS.
Due to this design a full DTB is added here as well that allows U-Boot's
driver to properly function. The DTB is appended at the end of the U-Boot
image and will be merged with the QEMU provided DTB.
In addition provide documentation how to use, enable binman to fabricate both
ROMs that are required to boot and add ACPI tables to make it full compatible
to the EDK2 reference implementation.
The board was tested using Fedora 40 Aarch64 Workstation. It's able
to boot from USB and AHCI or network.
Tested and found working:
- serial
- PCI
- xHCI
- Bochs display
- AHCI
- network using e1000e
- CPU init
- Booting Fedora 40
1: Server Base System Architecture (SBSA)
2: https://www.qemu.org/docs/master/system/arm/sbsa.html
Signed-off-by: Patrick Rudolph <[email protected]>
Cc: Peter Robinson <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Tom Rini <[email protected]>
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Fill the MADT table in the GIC driver and armv8 CPU driver to
drop SoC specific code. While the GIC only needs devicetree
data, the CPU driver needs additional information stored in
the cpu_plat struct.
While on it update the only board making use of the existing
drivers and writing ACPI MADT in mainboard code.
TEST: Booted on QEMU sbsa-ref using GICV3 driver model generated MADT.
Booted on QEMU raspb4 using GICV2 driver model generated MADT.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Simon Glass <[email protected]>
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Support reading the "interrupts" property from the devicetree in case
the "interrupts-extended" property isn't found. As the "interrupts"
property is commonly used, this allows to parse all existing FDT and
makes irq_get_by_index() more useful.
The "interrupts" property doesn't contain a phandle as "interrupts-extended"
does, so implement a new method to locate the interrupt-parent called
irq_get_interrupt_parent().
TEST: Read the interrupts from the GIC node for ACPI MADT generation.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Moritz Fischer <[email protected]>
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Add a generic GICV2 driver that:
- parses the DT and generates the ACPI MADT subtables
- implement of_xlate() and allows irq_get_by_index() to return the
correct interrupt mappings
Map DT interrupts to ARM GIC interrupts as follows:
- Interrupt numbers ID32-ID1019 are used for SPIs
- ID0-ID15 are used for SGIs
- ID16-ID31 are used for PPIs
TEST: Booted on QEMU raspb4 using GICV2 driver model generated MADT.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Translate IRQs by implementing of_xlate() as required by
irq_get_by_index() to parse interrupt properties.
Map DT interrupts to ARM GIC interrupts as follows:
- Interrupt numbers ID32-ID1019 are used for SPIs
- ID0-ID15 are used for SGIs
- ID16-ID31 are used for PPIs
TEST: Booted on qemu sbsa-ref that has a GICV3.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Moritz Fischer <[email protected]>
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The code accesses the gic-v3 node, but not the gic-v3-its node,
thus rename the objects to clarify which node it operates on.
The following commit will make use of the gic-v3-its node for real.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Allow other architectures to use acpi_create_mcfg_mmconfig as well
by moving the function prototype to common code.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Simon Glass <[email protected]>
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The FADT structure found in U-Boot represents FADT revision 6 and the
GICC and GICD structures defined in U-Boot are based on ACPI revision
6.3.
Bump the table revision to fix FWTS failures seen on aarch64.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
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Add a new method to acpi_ops to let drivers fill out ACPI MADT.
The code is unused for now until drivers implement the new ops.
TEST: Booted on QEMU sbsa using driver model generated MADT.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Simon Glass <[email protected]>
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Add generic ACPI code to generate
- MADT GICC
- MADT GICD
- MADT GICR
- MADT GIC ITS
- PPTT processor
- PPTT cache
as commonly used on arm platforms.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Simon Glass <[email protected]>
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Write MADT in common code and let the SoC fill out the body by
calling acpi_fill_madt() which must be implemented at SoC level.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
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Write the FADT in common code since it's used on all architectures.
Since the FADT is mandatory all SoCs or mainboards must implement the
introduced function acpi_fill_fadt() and properly update the FADT.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
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This moves the SPCR and DBG2 table generation into common code, so that
they can be used by architectures other than x86.
Signed-off-by: Maximilian Brune <[email protected]>
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/22993
- New boards:
rk3566: Hardkernel ODROID-M1S
rk3588s: Hardkernel ODROID-M2
rk3588: NanoPC-T6 LTS
- Migrate to use USB_DWC3_GENERIC for rk3328
- Other board level config and dts update
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Update defconfig to enable features included in pending upstream DT and
implement board_fit_config_name_match() to load correct DT for LTS and
non-LTS version of the NanoPC-T6.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The SPI flash node has been added in upstream DT, drop all props beside
bootph-* props from the SPI flash related nodes from u-boot.dtsi.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The SPI flash node has been added in upstream DT, drop all props beside
bootph-* props from the SPI flash related nodes in u-boot.dtsi.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The SPI flash node has been added in upstream DT, drop all props beside
bootph-* props from the SPI flash related nodes in u-boot.dtsi.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Increase rng-seed size to make Linux happy and initialize rng pool instantly.
Linux 5.19+ requires 32 bytes of entropy to initialize random pool, but u-boot
currently provides only 8 bytes.
Linux 5.18 and probably some versions before it used to require 64 bytes.
Bump min value to 64 bytes to be on a safe side.
Boot with 8 byte rng-seed (Linux 6.11):
# dmesg | grep crng
[ 12.089286] random: crng init done
Boot with 32 byte rng-seed (Linux 6.11):
# dmesg | grep crng
[ 0.000000] random: crng init done
Linux source references:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/char/random.c?h=v5.19#n551
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/char/random.c?h=v5.18#n236
Signed-off-by: Alex Shumsky <[email protected]>
Fixes: d2048bafae40 ("rockchip: board: Add board_rng_seed() for all Rockchip devices")
Reviewed-by: Dragan Simic <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22989
- Remove unneeded USB board code and fix reset on mx6ul_14x14_evk.
- Update fastboot buffer size/address for verdin-imx8m{m|p}.
- Fix imxrt1050-evk boot and convert it to standard boot.
- Fix imx8qxp-mek and imx8qm-mek boot.
- Add support for the i.MX93 9X9 QSB board.
- Make livetree API to work on i.MX.
- Set sane default value for i.MX8M SPL_LOAD_FIT_ADDRESS.
- Deduplicate DH i.MX8MP/i.MX6 DHSOM defconfigs.
- Select default TEXT_BASE for i.MX6/i.MX7.
- Several updates for DH i.MX8MP DRC02.
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Move i.MX7 TEXT_BASE/SPL_TEXT_BASE to Kconfig and common/spl/Kconfig
which is the best practice.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Add #address-cells and #size-cells to the memory node to fix warnings
Signed-off-by: Jesse Taube <[email protected]>
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Two of the clocks required by the usdhc1 controller are missing from the
clock controller node. A recent change enables all the clocks in the
esdhc node, which fails as they are not defined in the clock controller.
Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API")
Signed-off-by: Jesse Taube <[email protected]>
Cc: Peng Fan <[email protected]>
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The Hardkernel ODROID-M1S is a single-board computer based on Rockchip
RK3566 SoC. It features e.g. 4/8 GB LPDDR4 RAM, 64 GB eMMC, SD-card,
GbE LAN, HDMI 2.0, M.2 NVMe and USB 2.0/3.0.
Features tested on a ODROID-M1S 8GB rev1.0 20230906:
- SD-card boot
- eMMC boot
- Ethernet
- PCIe/NVMe
- USB gadget
- USB host
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Hardkernel ODROID-M2 is a single-board computer based on Rockchip
RK3588S2 SoC. It features e.g. 8/16 GB LPDDR5 RAM, 64 GB eMMC, SD-card,
GbE LAN, HDMI 2.0, M.2 NVMe and USB 2.0/3.0/Type-C.
Features tested on a ODROID-M2 16GB rev1.0 20240611:
- SD-card boot
- eMMC boot
- Ethernet
- PCIe/NVMe
- USB gadget
- USB host
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Allow to disable serial console in SPL. Weak dependency is already used
with TPL serial.
Signed-off-by: Daniel Semkowicz <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable the PD_VO power domain before driver access on the rk3568 SoC.
Signed-off-by: Chris Morgan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Refactor the board detection logic (again) to make it compatible with
the upstream device-trees, and switch to OF_UPSTREAM.
Now the device boots with the device-tree for the 353P, and then
loads the correct device tree (of 10) in the later stages of SPL.
Signed-off-by: Chris Morgan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add dedicated getter and setter for SCLK_UART0_PMU.
This allows the driver to correctly handle UART0 clocks, and thus
it fixes the issues with UART0 not working in case DEBUG_UART is
disabled.
Unlike other Rockchip SoCs, i.e. rk3399, in the PX30 the default
clock source for UART is GPLL, instead of external oscillator.
If the DEBUG_UART is enabled, the clock source is changed in
board_debug_uart_init function to 24Mhz oscillator, which also
matches the fallback value obtained from DT node.
In case the DEBUG_UART is disabled, the UART clock source remains
default, and the DM serial driver wrongly configures the baud rate,
resulting in broken communication.
By implementing the UART clock getter/setter, the serial driver
can probe the actual configuration and corectly configure itself.
The DEBUG_UART settings now should not affect it.
The driver supports GPLL and 24M oscillator. NPLL and USBPHY480M
sources, that are managed by CRU, are not yet handled, as likely
they won't be used in real scenarios.
Signed-off-by: Lukasz Czechowski <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Basically, Radxa's boards are intended to turn LEDs on at U-Boot.
add `default-state = "on"` to u-boot.dtsi.
Signed-off-by: FUKAUMI Naoki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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ROCK Pi 4 series and ROCK 4C+ cannot share .dtsi file because 4C+ is
different board.
add rk3399-rock-pi-4-u-boot.dtsi contents and remove dependency of it.
no functional change is intended.
Fixes: 71a95e2efd30 ("arm: dts: rockchip: add Radxa ROCK 4C+")
Suggested-by: Dragan Simic <[email protected]>
Signed-off-by: FUKAUMI Naoki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Fix the issue introduced by commit fed064477c2c
("arm64: zynqmp: Print an error for split to lock mode switch").
The mini u-boot is hanging, because of the tcm is not initialized.
The mini u-boot is using the tcm to reserve the mmu table and
currently it is not initialized, so allowing u-boot to initialize
the tcm.
Signed-off-by: Padmarao Begari <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Fix pointers to incorrect file name described in DT.
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/6e6017ad613d452d16ce0f7fba8a6ce32b174413.1727247725.git.michal.simek@amd.com
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U-Boot code is not reading this variable that's why remove it from DT.
PL011 code is automatically using CONFIG_BAUDRATE instead.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/3de28cc8bbf9571d24673a60809c2075fe2f44c3.1727247837.git.michal.simek@amd.com
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