| Age | Commit message (Collapse) | Author |
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Move env to imx8mm_evk.env
Switch to support BOOTSTD with a bsp bootcmd as fallback.
Signed-off-by: Peng Fan <[email protected]>
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Move env to imx8mp_evk.env.
Switch to support BOOTSTD with a bsp bootcmd as fallback.
Signed-off-by: Peng Fan <[email protected]>
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Switch to support BOOTSTD with a bsp bootcmd as fallback.
Signed-off-by: Peng Fan <[email protected]>
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Switch to support BOOTSTD with a bsp bootcmd as fallback.
Signed-off-by: Peng Fan <[email protected]>
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Switch to support BOOTSTD with a bsp bootcmd as fallback.
Move the env to imx93_evk.env
Signed-off-by: Peng Fan <[email protected]>
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Add Canaan K230 SoC with sysreset support, running without cache
enabled.
Signed-off-by: Junhui Liu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add initial dts for K230-CanMV powered by Canaan Kendryte K230 SoC,
which has two RISC-V C908 cores, a big core with vector 1.0 extension
and a small core without vector extension.
This patch is basically comes from Linux Kernel [1] and it assumes
u-boot is running on the big core. Additionally, bootctl and reboot nodes
are added to support sysreset [2] and an clk_dummy node is added to
satisfy dependencies for usb [3].
Currently, u-boot is booted by the vendor's u-boot-spl. To meet the
requirements [4][5] of vendor's u-boot-spl for u-boot, a binman node with
mkimage child node is added here, which will compress u-boot.bin with
gzip and generate an image named "uboot" in the file u-boot-gz.img.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=k230-basic
[2] https://github.com/kendryte/k230_sdk/blob/v1.8/src/big/rt-smart/kernel/bsp/maix3/board/interdrv/sysctl/sysctl_boot/sysctl_boot.c#L67
[3] https://lore.kernel.org/linux-riscv/[email protected]/
[4] https://github.com/kendryte/k230_sdk/blob/v1.8/src/little/uboot/board/canaan/common/k230_img.c#L306
[5] https://github.com/kendryte/k230_sdk/blob/v1.8/src/little/uboot/board/canaan/common/k230_img.c#L125
Signed-off-by: Junhui Liu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The RISC-V ISA profile RVA23U64 requires extension Zic64b (Cache blocks
must be 64 bytes in size, naturally aligned in the address space).
Some RISC-V platforms do not define the d-cache line size through SYS_CACHE_SHIFT_n.
Set a default value of 64 bytes for such cases.
Signed-off-by: Yu-Chien Peter Lin <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Update the cpu probing to fallback to "riscv,isa" property if
"riscv,isa-extensions" is not available and modify the riscv CMO code
to use the block size that was probed during cpu setup.
Signed-off-by: Mayuresh Chitale <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Enhance the existing extension probing mechanism by adding support for
more extensions and probing using the "riscv,isa" property. This patch
is ported from the latest upstream linux.
Signed-off-by: Mayuresh Chitale <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Split out StarFive VisionFive2 multi-board target specific configuration
into starfive-visionfive2-binman.dtsi in preparation for removal of
jh7110-u-boot and jh7110-common-u-boot in part or whole as sent upstream.
Signed-off-by: E Shattow <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Aparna Patra <[email protected]> says:
This series implements fdt fixups, by reading hardware
information from registers and accordingly delete/modify
the DT nodes, at run-time.
Logs for AM62P boot:
https://gist.github.com/itsme-aparna/b889fe59882c1acf0ef25a644bd325c4
Link: https://lore.kernel.org/r/[email protected]
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The maximum frequency of the A53 CPU on the AM62P depends on the speed
grade of the SoC. This value is hardcoded in the DT for all AM62P
variants, potentially causing specifications to be exceeded. Moreover,
setting a common lower frequency for all variants increases boot time.
To prevent these issues, modify the DT at runtime from the R5 core to
adjust the A53 CPU frequency.
Signed-off-by: Aparna Patra <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
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AM62P SoC has multiple speed grades. Add function to delete
non-relevant CPU frequency nodes, based on the information
retrieved from hardware registers. Fastest grade's maximum
frequency also depends on PMIC voltage, hence to simplify
implementation use the smaller value.
Signed-off-by: Aparna Patra <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
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Read the max temperature for the SoC temperature grade from the hardware
and modify the critical trip nodes on each thermal zone of FDT at
runtime so they are correct with the hardware value for its grade.
Signed-off-by: Aparna Patra <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
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AM62P SOC is available in multiple variants:
-CPU cores (Cortex-A) AM62Px1 (1 core),
AM62Px2 (2 cores), AM62Px4 (4 cores)
-With and without CAN-FD & Video-codec support
Remove the relevant FDT nodes by reading the actual configuration
from the SoC registers, with that change it is possible to have a single
dts/dtb file handling the different variant at runtime.
Signed-off-by: Aparna Patra <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
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Santhosh Kumar K <[email protected]> says:
Hello,
This series adds support for Inline ECC in DDR for AM64X, AM62X,
AM62AX, AM62PX, J721E, J721S2, J722S and J784S4 devices.
Test Results: https://gist.github.com/santhosh21/88de920771ed2efa0463a5a367cb8d7b
Link: https://lore.kernel.org/r/[email protected]
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size when ECC is enabled
As there are few redundant functions in board/ti/*/evm.c files, pull
them to a common location of access to reuse and include the common file
to access the functions.
Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the
device tree and resize the available amount of DDR, if ECC is enabled.
Otherwise, fixup the device tree using the regular
fdt_fixup_memory_banks().
Also call dram_init_banksize() after every call to
fixup_ddr_driver_for_ecc() is made so that gd->bd is populated
correctly.
Ensure that fixup_ddr_driver_for_ecc() is agnostic to the number of DDR
controllers present.
Signed-off-by: Santhosh Kumar K <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
Reviewed-by: Wadim Egorov <[email protected]>
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Set CONFIG_NR_DRAM_BANKS to 2 as we have two banks described in the
memory/ node for lower and higher addressible DDR regions.
This allows use of FDT functions from fdt_support.c to set up and fix up
the memory/ node correctly.
Signed-off-by: Neha Malcom Francis <[email protected]>
Signed-off-by: Santhosh Kumar K <[email protected]>
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Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K <[email protected]>
Signed-off-by: Neha Malcom Francis <[email protected]>
Tested-by: Neha Malcom Francis <[email protected]>
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Raymond Mao <[email protected]> says:
Motivations for changes:
Current SMBIOS library and command-line tool is not fully matching with
the requirements:
1. Missing support for other mandatory types (#7, #9, #16, #17, #19).
2. Only a few platforms support SMBIOS node from the device tree.
3. Values of some fields are hardcoded in the library other than fetching
from the device hardware.
4. Embedded data with dynamic length is not supported (E.g. Contained
Object Handles in Type #2 and Contained Elements in Type #3)
Changes:
1. Refactor the SMBIOS library and command-line tool to better align with
the SMBIOS spec.
2. Create an arch-specific driver for all aarch64-based platforms to fetch
SMBIOS private data from the device hardware (processor and cache).
3. Create a sysinfo driver to poppulate platform SMBIOS private data.
4. Add generic SMBIOS DTS file for arm64 platforms for those common strings
and values which cannot be retrieved from the system registers.
Vendors can create their own SMBIOS node using this as an example.
For those boards without SMBIOS nodes, this DTS file can be included to
have a generic SMBIOS information of the system.
5. Add support for Type #7 (Cache Information) and link its handles to
Type #4.
6. To minimize size-growth for those platforms which have not sufficient
ROM spaces or the platforms which don't need detailed SMBIOS
information, new added fields are only being built when kconfig
GENERATE_SMBIOS_TABLE_VERBOSE is selected.
Once this patch is acceptted, subsequent patch sets will add other missing
types (#9, #16, #17, #19).
Tests:
To test this with QEMU arm64, please follow the guide on dt_qemu.rst to
get a merged DT to run with.
```
qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb
cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb ./dts/dt.dtb | grep -v /dts-v1/) \
| dtc - -o merged.dtb
qemu-system-aarch64 -machine virt -nographic -bios u-boot.bin \
-dtb merged.dtb
```
Link: https://lore.kernel.org/r/[email protected]
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Add common smbios information that can be used by all armv8
platforms and set it as default for qemu-arm64.
>From now smbios library can load values from here for those fields
doesn't exist in the sysinfo driver.
To run this with QEMU arm64, we need to dump the generated DTB
from QEMU first, merge it with the one we build and then re-run
QEMU with the merged DTB.
```
qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb
cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb ./dts/dt.dtb | \
grep -v /dts-v1/) | dtc - -o merged.dtb
qemu-system-aarch64 -machine virt -nographic -bios u-boot.bin \
-dtb merged.dtb
```
For details please take reference on dt_qemu.rst
Signed-off-by: Raymond Mao <[email protected]>
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Add sysinfo platform driver for all armv8 platforms to retrieve
hardware information on processor and cache.
Signed-off-by: Raymond Mao <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Label all eeproms so we can open by label rather than a fixed i2c address.
Signed-off-by: Jonathan Stroud <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/878558c3c859599d29bc4ae2278baebf84b368e0.1736152966.git.michal.simek@amd.com
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Description is coming from SOM only that's why enable it only on SOM.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/08ee4ce2fe242905dd99cea2b87373b57d8fea91.1736152939.git.michal.simek@amd.com
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Sync zynqmp* DTS files with v6.13-rc1 Linux kernel including three patches
from Sean:
arm64: zynqmp: Enable AMS for all boards
arm64: zynqmp: Expose AMS to userspace as HWMON
arm64: zynqmp: Add thermal zones
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/06e466d64c9d8e718e2f06a76cc65d6da2a37a7b.1733996500.git.michal.simek@amd.com
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Replace underscores with hyphens in the clock node names as per
dt-schema rule.
Also, add clock-output-names property to all clock nodes, so that the
resulting clock name do not change when clock node name is changed.
Signed-off-by: Naman Trivedi <[email protected]>
Acked-by: Senthil Nathan Thangaraj <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/1080e31393c3e1b49735b77e7ddc14d570b83222.1733991159.git.michal.simek@amd.com
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multi_boot is already the part of csu_base structure that's why use it
directly instead of using register offset value.
Fixes: fc001432e5b0 ("arm64: zynqmp: Add u-boot command to boot into recovery image")
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/3e5c6ea426b81cc73b90e6425764e41a98deb2a6.1733735454.git.michal.simek@amd.com
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Add MIDR entries for Cortex-A57 and Cortex-A76 cores.
Those are used on R-Car Gen3 and Gen4 SoCs respectively.
Reviewed-by: Paul Barker <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Turn the core type check macros into inline functions to perform
better type checking on them. The inline functions get optimized
out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An
macros in preparation for addition of future three-digit cores
and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent.
Reviewed-by: Paul Barker <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Implement checkboard() to print current SoC variant used by a board,
e.g. one of:
SoC: RK3308
SoC: RK3308B
SoC: RK3308B-S
when U-Boot proper is running.
U-Boot 2025.01-rc1 (Nov 02 2024 - 20:26:25 +0000)
Model: Radxa ROCK Pi S
SoC: RK3308B
DRAM: 512 MiB (effective 510 MiB)
Information about the SoC variant is read from GRF.
Signed-off-by: Jonas Karlman <[email protected]>
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Implement checkboard() to print current SoC model used by a board,
e.g. one of:
SoC: RK3582
SoC: RK3588
SoC: RK3588J
SoC: RK3588S
SoC: RK3588S2
when U-Boot proper is running.
U-Boot 2025.01-rc1 (Nov 10 2024 - 00:31:29 +0000)
Model: Generic RK3588S/RK3588
SoC: RK3588S2
DRAM: 8 GiB
Information about the SoC model and variant is read from OTP.
Also update rk3588s-u-boot.dtsi to include OTP in U-Boot pre-reloc phase,
where checkboard() is called.
Signed-off-by: Jonas Karlman <[email protected]>
Tested-by: FUKAUMI Naoki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Implement checkboard() to print current SoC model used by a board,
e.g. one of:
SoC: RK3566
SoC: RK3566T
SoC: RK3568
SoC: RK3568B2
SoC: RK3568J
when U-Boot proper is running.
U-Boot 2025.01-rc1 (Nov 10 2024 - 00:39:37 +0000)
Model: Generic RK3566/RK3568
SoC: RK3568J
DRAM: 8 GiB (effective 7.7 GiB)
Information about the SoC model and variant is read from OTP.
Also update rk356x-u-boot.dtsi to include OTP in U-Boot pre-reloc phase,
where checkboard() is called.
Signed-off-by: Jonas Karlman <[email protected]>
Tested-by: FUKAUMI Naoki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The mask for aclk_vop_root is 3-bit wide, not 2-bit wide according
to the TRM, so set the mask accordingly.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The commit 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for
NanoPC-T6 LTS") added support for the LTS variant of NanoPC T6. However,
a board specific -u-boot.dtsi file was never added.
Due to the missing -u-boot.dtsi file the LTS fdt included in the FIT is
never tagged with bootph props.
When ENV_IS_IN_SPI_FLASH is enabled, not enabled in defconfig, the env
can successfully load from SPI flash on the non-LTS variant, something
that does not work on the LTS variant due to missing bootph-some-ram
props in the LTS fdt.
Fix this by adding a LTS -u-boot.dtsi file that just include the non-LTS
-u-boot.dtsi file.
Reported-by: Ricardo Pardini <[email protected]>
Fixes: 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for NanoPC-T6 LTS")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The IO-domain driver will configure io_vsel and always-on/boot-on
regulators will be enabled based on the board device tree now that
required nodes and Kconfig options is enabled for SPL.
Remove the bob and kevin board specific code from the common rk3399.c,
the IO-domain and regulator driver provide similar functionality.
Signed-off-by: Jonas Karlman <[email protected]>
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Add bootph props and enable related Kconfig options to include vital
regulators in SPL.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The eMMC PHY and SPI flash is not used in all xPL phases.
Change to no longer include emmc_phy and spi_flash in all xPL phases.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The last two RK3399 boards, chromebook bob and kevin, have now migraded
to use common bss and stack addresses.
Cleanup and remove Kconfig options no longer needed in rk3399/Kconfig
when all boards now use common bss and stack addresses.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The u-boot.rom image contain u-boot.img FIT instead of the FIT generated
by binman for the u-boot-rockchip.bin image.
Change to include the binman generated FIT for the u-boot.rom image.
This change result in TF-A being included and the use sha256 instead of
crc32 checksum in the u-boot.rom FIT.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The chromebook specific u-boot.rom image does not include TPL when
building with TPL=y or ROCKCHIP_EXTERNAL_TPL=y.
Fix this by adding rockchip-tpl and u-boot-tpl nodes to the mkimage node
for the u-boot.rom binman image.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Use the offset configured with SYS_SPI_U_BOOT_OFFS Kconfig option
instead of a hardcoded 0x40000 for the FIT payload offset.
This has no intended impact as SYS_SPI_U_BOOT_OFFS=0x40000.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Building chromebook_bob/kevin with TPL=y ends with a linking error:
arch/arm/mach-rockchip/rk3399/rk3399.o: in function `board_debug_uart_init':
arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34):
undefined reference to `spl_gpio_output'
arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `spl_gpio_output'
make[2]: *** [scripts/Makefile.xpl:542: tpl/u-boot-tpl] Error 1
make[1]: *** [Makefile:2134: tpl/u-boot-tpl] Error 2
make: *** [Makefile:568: __build_one_by_one] Error 2
Change to only use spl_gpio functions in SPL to fix this.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The device tree for rk3066a/rk3188 combined is now
available in the /dts/upstream directory.
Use imply OF_UPSTREAM to migrate all rk3066a/rk3188 boards.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Radxa ROCK 5C[1] is a Rockchip RK3588S2 based single board computer.
[1] https://radxa.com/products/rock5/5c
Signed-off-by: FUKAUMI Naoki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
Ethernet ports designed and developed by FriendlyElec for IoT
applications.
Specification:
- Rockchip RK3566
- 2GB LPDDR4X RAM
- optional 32GB eMMC module
- SD card slot
- 2x 1000 Base-T
- 3x LEDs (POWER, LAN, WAN)
- 2x Buttons (Reset, MaskROM)
- 1x USB 3.0 Port
- Type-C 5V 2A Power
Signed-off-by: Tianling Shen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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Migrate to use common bss, stack and malloc heap size and addresses to
unify memory use in TPL, SPL and pre-reloc.
Ensure SYS_MALLOC_F_LEN and TPL variant stay at 0x2000 and is unaffected
on other boards not changed to use common malloc heap size.
ENV_OFFSET is using the default value of 0x3f8000 and is also dropped.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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For some reason the Ethernet PHY reset delay is set to 1 second, this
cause an unneccecery long boot delay.
Firefly-RK3288 use RTL8211 Ethernet PHY, datasheet list an initial 10ms
delay and then a 30-76ms delay before accessing registers.
Change to use 80ms delay instead of a full second to speed up Ethernet
initializion in U-Boot.
Also enable PHY_REALTEK, DM_ETH_PHY and PHY_GIGE to improve Ethernet PHY
support in U-Boot.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The device tree for Firefly-RK3288 in dts/upstream can be used as-is by
U-Boot, migrate board to use OF_UPSTREAM.
Add chosen stdout-path prop to board u-boot.dtsi as it is missing in DT
from dts/upstream. Also change to use the upstream power_led symbol.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Include mmc related nodes in U-Boot proper pre-reloc phase to ensure
environment can be loaded from mmc devices.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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