| Age | Commit message (Collapse) | Author |
|---|
|
There are still two places in Quark's MRC codes that use the generic
legacy PCI APIs, but as we are phasing out these legacy APIs, switch
to use Quark's own PCI config routines.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Now that we have converted all x86 codes to use DM PCI APIs,
drop those legacy ones.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
Drop legacy PCI APIs usage in pci_assign_irqs() as well.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
Use pci_[read|write]_config intead of x86_pci_[read|write]_config.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
With recent DM PCI changes to vesa_fb driver, external graphics
card does not work any more. This is because: after setting the
function disable bit, IGD and SDVO devices will disappear in the
PCI configuration space. This however creates an inconsistent state
from a driver model PCI controller point of view, as these two PCI
devices are still attached to its parent's child device list as
maintained by the driver model. Some driver model PCI APIs like
dm_pci_find_class() used in the vesa_fb driver, are referring to
the list to speed up the finding process instead of re-enumerating
the whole PCI bus, so it gets the stale cached data which is wrong.
To fix this, manually remove these two devices.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
Once we get udevice of IGD and SDVO, we can use its udevice to
access PCI configuration space with dm_pci_write_config32().
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
So far disable_igd() does not have any return value, but we may need
that in the future.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
Now that we have irq router's udevice passed as a parameter, it's
time to start using the DM PCI API instead of those legacy ones.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
At present irq_router is declared as a static struct irq_router in
arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense
to move it to a per driver priv. Adjust existing APIs to accept an
additional parameter of irq_router's udevice.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
There is no need to parse PCH's <reg> property as we have already
a DM PCI API dm_pci_get_bdf() that can handle this.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
IOBASE is now obtained from PCH driver, drop this <io-base> property.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
asm/arch/gpio.h is not needed anymore as we get the GPIO base from
PCH driver.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While the device tree has nodes for the GPIO peripheral it is
not in the right place. It should be on the PCI bus as a sub-peripheral
of the PCH device.
Update the device tree files to show the GPIO controller within the PCH,
so that PCI access works as expected. This also adds '#address-cells'
and '#size-cells' to the PCH node.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
Spell out 'sbase' to 'spi_base' so that it looks clearer.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
pch_get_version op was only used by the ich spi controller driver,
and does not really provide a good identification of pch controller
so far, since we see plenty of Intel PCH chipsets and one differs
from another a lot, which is not simply either a PCHV_7 or PCHV_9.
Now that ich spi controller driver was updated to not get such info
from pch, the pch_get_version op is useless now.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatible string.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
Implement mmc_get_env_dev, devno can be got from smbr1 of SRC.
Introduce a weak function board_mmc_get_env_dev, different
boards can implement it according to different sdhc controllers
that used by the board.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
|
|
Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to
match the one in common/env_mmc.c.
Introduce a weak function board_mmc_get_env_dev. Different
boards can implement this according to sdhc controller which
is used by the board.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
|
|
- Add device tree files for Phytec phyCORE-Vybrid Board.
- Enable lpuart support for Phytec phyCORE-Vybrid Board.
- Use UART1 for stdout.
Signed-off-by: Bhuvanchandra DV <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
- Add device tree files for NXP/Freescale VF610 Tower Board.
- Enable lpuart support on NXP/Freescale VF610 Tower Board.
- Use UART1 as stdout.
Signed-off-by: Bhuvanchandra DV <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
- Enable lpuart support on Toradex Colibri VF50/VF61
- Use UART0 for stdout.
Signed-off-by: Bhuvanchandra DV <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Since SPDX license is already there, drop the full one.
Signed-off-by: Bhuvanchandra DV <[email protected]>
Acked-by: Stefan Agner <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Add device tree node's for lpuart on Vybrid platform
Signed-off-by: Bhuvanchandra DV <[email protected]>
Acked-by: Stefan Agner <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
The checking with max frequency supported is not correct, because the temp
is calculated by max pre and post dividers. We can decrease any divider to
meet the max frequency limitation. Actually, the calculation below the codes
is doing this way to find best pre and post dividers.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
|
|
Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always
enter the -EINVAL return.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
|
|
Initial version for mx6sx SABREAUTO board support with features:
PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.
Signed-off-by: Ye Li <[email protected]>
|
|
The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
MAC address from fuse for ENET2.
Signed-off-by: Ye Li <[email protected]>
|
|
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
|
|
|
|
|
|
The sama5d2 Xplained SPL supports the boot medias: spi flash
and SD Card.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
|
|
To remove the unnecessary #ifdef-endif, use the mpddrc IP version
to check whether or not the interleaved decoding type is supported.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
|
|
The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the SAMA5D2 datasheet.
Add registers and definitions of mpddrc controller, which is used
to support DDR3 devices.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
|
|
Add struct atmel_mpddrc_config to accommodate the mpddrc register
configurations, not using the mpddrc register map structure,
struct atmel_mpddrc, in order to increase readability and reduce
run-time memory use.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
|
|
Valid for core A57
Signed-off-by: Ashish Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
|
|
829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.
833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.
Signed-off-by: Ashish Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.
Signed-off-by: Purna Chandra Mandal <[email protected]>
|
|
Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.
Signed-off-by: Purna Chandra Mandal <[email protected]>
|
|
This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.
Signed-off-by: Purna Chandra Mandal <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
|
|
Add Microchip PIC32MZ[DA] SoC family support.
Signed-off-by: Purna Chandra Mandal <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
|
|
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).
Signed-off-by: Paul Thacker <[email protected]>
Signed-off-by: Purna Chandra Mandal <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.
Signed-off-by: Purna Chandra Mandal <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
The existing mips_io_port_base variable isn't suitable for use early
during boot since it will be stored in the .data section which may not
be writable pre-relocation. Fix this by moving the I/O port base address
into struct arch_global_data. In order to avoid adding this field for
all targets, make this dependant upon a new Kconfig entry
CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a
non-zero I/O port base, so select this option only for Malta.
Signed-off-by: Paul Burton <[email protected]>
|
|
CONF_SLOWDOWN_IO is never set for any target, so remove the dead code in
the SLOW_DOWN_IO macro. This is done in preparation for changes to
mips_io_port_base which can be avoided in this path by removing it
entirely.
Signed-off-by: Paul Burton <[email protected]>
|
|
This patch makes sure that the flush/invalidate_dcache_range() functions
can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
This call is valid and is happily produced by USB EHCI code for example.
The expected behavior of the cache function(s) in this case is that they
will do no operation, since the size is zero.
The current implementation though has a problem where such invocation will
result in a hard CPU hang. This is because under such conditions, where the
start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop
will then try to iterate over the entire address space, which in itself is
wrong. But iterating over the entire address space might also hit some odd
address which will cause bus hang. The later happens on the Atheros MIPS.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Cc: Hans de Goede <[email protected]>
|
|
Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as
32 Bit register. Use 64 Bit register access for clearing gd_data
and copying U-Boot.
Signed-off-by: Daniel Schwierzeck <[email protected]>
|
