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since different rockchip SOC have different size of SRAM,
So the size SYS_MALLOC_F_LEN may different, so move this
config to rk3288 own Kconfig
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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At the moment, the desired brownout is at 1.0V. However,
this setting cannot be realized by hardware since we have
only 3 bits to represent the voltage difference from the
target value.
Target value is 1500 mV, brownout target is 1000 mV,
voltage steps are 25 mV.
Register content calculation:
(1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14
Register takes only 3 bits, that is 0x4.
But 0x4 * 25 [mV] = 100 [mV], that means that actual
brownout level is 1500 [mV] - 100 [mV] = 1.4 V.
Minimum possible BO level is
1500 [mV] - 0x7 * 25 [mV] = 1315 [mV].
So lets use this value as desired BO value (which is
also the same as FSL bootlets use).
Signed-off-by: Michael Heimpold <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Fabio Estevam <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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This makes it easier to select common options in a single place, rather
than having to add them separately for different SoCs or architectures.
The lists of select statements are now also sorted for easy searching.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Simon Glass <[email protected]>
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To group all dm timer drivers together, move tsc timer to
drivers/timer directory.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Now that we have converted all x86 boards to use driver model timer,
remove these legacy timer codes in the tsc driver.
Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option,
as it is not needed with driver model.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Convert all x86 boards to use driver model tsc timer.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This adds driver model timer support to x86 tsc timer driver.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Replace __attribute__((no_instrument_function)) with notrace from
<linux/compiler.h>.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This is not referenced anywhere. Remove it, as well as
tsc_base_kclocks and tsc_prev in the global data.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Fix 'Reomve' typo:
Signed-off-by: Simon Glass <[email protected]>
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We should use device tree to pass the clock frequency of the timer
instead of hardcoded in the driver codes.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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To make saic redirect code sharing with other SoCs, move the
saic redirect code from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/atmel_sfr.c
Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each
SoC has its own value.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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To make matrix initialization code sharing with others,
use the matrix slave id macros, instead of hard-coding.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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Remove the security peripheral select code, keep the default value
in these registers, that is, the peripheral address space is
configured as "Secured" access, it is suitable for SPL.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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On processor reset, the matrix write protection is disabled,
so no need to disable/enable write protection when writing
the matrix registers.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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To make the matrix initialization code sharing with other SoCs,
move it from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/matrix.c
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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The board supports following features:
- Boot media support: SD card/e.MMC/SPI flash,
- Support LCD display (optional, disabled by default),
- Support ethernet,
- Support USB mass storage.
Signed-off-by: Wenyou Yang <[email protected]>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <[email protected]>
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The PIO4 is introduced from SAMA5D2, as a new version
for Atmel PIO controller.
Signed-off-by: Wenyou Yang <[email protected]>
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The early MMU table doesn't enable all addresses. Unused addresses
are marked as invalid, as introduced by commit 9979922. An entry
was missing for NAND flash space, causing nand boot failure.
Signed-off-by: York Sun <[email protected]>
CC: Alison Wang <[email protected]>
CC: Prabhakar Kushwaha <[email protected]>
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If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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When one core is released, other cores may not have valid entry
address. Those cores are trapped by "wfe" and wait for further
instruction. When their address is set, they need to be kicked
off by "sev".
Signed-off-by: York Sun <[email protected]>
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For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Alison Wang <[email protected]>
Reported-by: Zhichun Hua <[email protected]>
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Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.
Signed-off-by: York Sun <[email protected]>
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Add support for the third USB controller for LS1043A.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Use the U-Boot Driver Model. Just enable Freescale DSPI driver
and set DSPI related parameters in dts file.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Reuse the dts files from ls1043a linux kernel.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS1043AQDS Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 DIMM
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* Two RGMII ports
* XFI 10G port
* SGMII
* QSGMII with 4x 1G ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <[email protected]>
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Reuse dts files from ls1043a linux kernel. Some parts in dts files
may not be needed by U-Boot.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The global_data pointer (gd) has been set earlier in crt0_64.S.
So there's no need to assign it again. Remove gdata since it is going
away in U-Boot.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <[email protected]>
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LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <[email protected]>
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Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.
Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Current implementation only consider SGMIIs for dpmac initialization.
XFI serdes protocols also uses dpmac.
Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch addresses a problem mentioned recently on this mailing list:
[1].
In that posting a LS1021 based system was locking up at about 5 minutes
after boot,but the problem was mysteriously related to the toolchain
used for building u-boot.Debugging the problem reveals a stuck
interrupt 29 on the GIC.
It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.This causes the timer compare to fire 344 seconds
after u-boot configures it.Depending on how fast u-boot gets the
kernel booted,this amounts to about 5-minutes of Linux uptime before
locking up.
Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
To fix the above issue, the generic physical timer is disabled
before jumping to the OS.
[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html
Signed-off-by: Chris Kilgour <[email protected]>
Signed-off-by: Alison Wang <[email protected]>
Acked-by: Mark Rutland <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch addresses a problem mentioned recently on this mailing list:
[1].
In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot. Debugging the problem reveals a stuck
interrupt 29 on the GIC.
It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value. This causes the timer compare to fire 344 seconds
after u-boot configures it. Depending on how fast u-boot gets the
kernel booted, this amounts to about 5-minutes of Linux uptime before
locking up.
Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
At any rate this patch makes the manipulation explicitly 64-bit which
alleviates the issue.
[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html
Signed-off-by: Chris Kilgour <[email protected]>
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Adding new node drvsel and smplsel for SDMMC
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Jaehoon Chung <[email protected]>
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This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Jan Viktorin <[email protected]>
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When adding support for the Arria10 platform, we're going to name the file
base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h
to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.
Suggested-by: Marek Vasut <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
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Add the base address map for Arria10.
Signed-off-by: Dinh Nguyen <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset
of the tstscratch register ist 0x54 not 0x24.
Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02
page 3-17 Reset Manager Module Address Map
Signed-off-by: Philipp Rosenberger <[email protected]>
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In preparation of some new Liebherr boards to be added soon, a new
"liebherr" vendor directory gets created, and the "lwmon5" board
directory is moved into this new vendor directory.
cc: Stefan Roese <[email protected]>
Signed-off-by: Wolfgang Denk <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The removal of some PPC4xx boards did not catch all references to
these boards. This patch now removes all remnants still left.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Stefan Roese <[email protected]>
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