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LS1043ARDB Specification:
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Memory subsystem:
* 2GByte DDR4 SDRAM (32bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G port
* QSGMII with 4x 1G ports
* Two RGMII ports
PCIe:
* PCIe2 (Lanes C) to mini-PCIe slot
* PCIe3 (Lanes D) to PCIe slot
USB 3.0: two super speed USB 3.0 type A ports
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Li Yang <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
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Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]
Signed-off-by: Horia Geantă <[email protected]>
Reviewed-by: Zhengxiong Jin <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Data types and I/O functions have been defined for
64 bit physical addresses in arm.
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled
in SD boot for QSPI. This patch will add fdt support for
this rule.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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My patches to drop various ppc4xx boards were not build tested and
omitted the Kconfig parts.
Signed-off-by: Tom Rini <[email protected]>
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be NULL
Pointer 'reg' returned from call to function 'fdt_getprop' may be
NULL, will be passed to function and may be dereferenced there by
passing argument 1 to function 'of_read_number'. So check pointer
'reg' first.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Enabled zynq qspi controller node for zed board.
Signed-off-by: Jagan Teki <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Acked-by: Michal Simek <[email protected]>
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Enabled zynq qspi controller node for zc770-xm010 board.
=> sf probe 0 -- bus1 for selecting qspi controller
=> sf probe 1 -- bus0 for selecting spi controller
Signed-off-by: Jagan Teki <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Acked-by: Michal Simek <[email protected]>
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Enabled zynq qspi controller node for zc706 board.
Signed-off-by: Jagan Teki <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Acked-by: Michal Simek <[email protected]>
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Enabled zynq qspi controller node for zc702 board.
Signed-off-by: Jagan Teki <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Acked-by: Michal Simek <[email protected]>
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Enabled zynq qspi controller node for microzed board,
verified the same on spansion spi-nor flash.
Signed-off-by: Jagan Teki <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Acked-by: Michal Simek <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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This patch adds zynq qspi controller nodes in zynq-7000.dtsi.
Signed-off-by: Jagan Teki <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Acked-by: Michal Simek <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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We have finished Generic Board conversion for ARM and PowerPC, i.e.
all the boards have been converted except OpenRISC, SuperH, SPARC,
which have not supported Generic Board framework yet.
Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro
defines in include/configs/*.h.
Signed-off-by: Masahiro Yamada <[email protected]>
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We should not init the console this early since it precludes using driver
model for the UART, since it is not set up at the start of board_init_f().
See the README for more information. The debug UART does not have this
restriction. If we want to do early init with the console on it can be done
in spl_board_init().
Move the preloader_console_init() call from board_init_f() to board_init_r().
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Masahiro Yamada <[email protected]>
Tested-by: Michal Simek <[email protected]>
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This C function should be used to do the early memory layout and init. This
is beyond my powers, so just add a TODO for the maintainer.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Michal Simek <[email protected]>
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There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.
Drop the unneeded code and adjust the hooks in board_f.c to cope.
Signed-off-by: Simon Glass <[email protected]>
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There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.
Drop the unneeded code and adjust the hooks in board_f.c to cope.
Tested on LS2085ARDB and LS2085AQDS (armv8 SoC).
Tested-by: York Sun <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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As the virtual address and physical address mapping of nios2 with
MMU are different. Add a check of MMU, and fix the mapping.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
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As we use device tree to control u-boot now, the generic
board can be removed.
Signed-off-by: Thomas Chou <[email protected]>
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Convert dma_alloc_coherent to use memalign.
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Convert copy_exception_trampoline() to use dm cpu data.
Signed-off-by: Thomas Chou <[email protected]>
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Convert cache flush to use dm cpu data.
The original cache flush functions are written in assembly
and use CONFIG_SYS_{I,D}CACHE_SIZE... macros. It is difficult
to convert to use cache configuration in dm cpu data which is
extracted from device tree.
The cacheflush.c of Linux nios2 arch uses cpuinfo structure,
which is very close to our dm cpu data. So we copy and modify
it to arch/nios2/lib/cache.c to replace the old cache.S.
Signed-off-by: Thomas Chou <[email protected]>
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Set default icache and dcache configuration for start.S.
We want to remove the CONFIG_SYS_{I,D}CACHE_SIZE...
configuration macros. As we are just barely starting from
reset, there is no luxury of device tree.
We will set some maximum cache configuration so that it will
work for most configurations. This is used only in this
start.S. The speed penalty is only once here.
After start up, during board initialization, cpu information
will be extracted from device tree. Then cache flush operations
will have correct cache configurations.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Clean up comments style in start.S.
Signed-off-by: Thomas Chou <[email protected]>
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Convert ioremap() to use io_region_base in dm cpu global data.
Also remove three unused io functions, which have style issue
and are replaced by macros already.
Signed-off-by: Thomas Chou <[email protected]>
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Convert do_reset to use dm cpu data.
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Remove asm/psr.h, which is not used.
Also clean up asm/sections.h and unaligned.h.
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Convert altera sysid to driver model with misc uclass.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Chin Liang See <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Convert altera timer to driver model.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Chin Liang See <[email protected]>
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Convert nios2 cpu to driver model. The cpu parameters are
extracted from device tree and saved to global data structure.
We will use them to replace the custom_fpga.h .
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Convert altera_pio to driver model.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Chin Liang See <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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These macros can be used to clear and set multiple bits
in a register using a single call.
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Acked-by: Chin Liang See <[email protected]>
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Convert altera_jtag_uart to driver model.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add ioremap() to map physical address to uncached virtual
address. We need this to convert the reg address from the
device tree.
The order of headers inclusion in interrupts.c is changed
because common.h will include board header that contains
IO_REGION_BASE.
In the future, the IO_REGION_BASE should be decided from
the device tree.
tree
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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We will need CONFIG_SYS_MALLOC_F_LEN to use serial uclass.
So we shall undefine CONFIG_SYS_GENERIC_GLOBAL_DATA, and
call board_init_f_mem() to allocates early malloc() memory
with size of CONFIG_SYS_MALLOC_F_LEN in board_f.c.
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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There is a weak version_string[] at common/cmd_version.c .
Remove the one in start.S.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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The dly_clks() in start.S is no use after switching to
generic timer. Remove it.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Move the timer code from interrupts.c into timer.c . Eliminate the
installation of timer interrupt handler, which is no longer used.
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Thomas Chou <[email protected]>
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Zap almost all of the ad-hoc timer code from interrupts.c and
use the code in lib/time.c instead.
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Thomas Chou <[email protected]>
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This patch adds device tree control of U-Boot to nios2 boards.
The example dts is taken from Linux kernel.
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Since commit 44c6e6591cb451ae606f8bde71dd5fb7b4002544
"rename _end to __bss_end__" , the _end was removed.
But we need it now for separated device tree control,
ie, CONFIG_OF_SEPARATE .
The _end is used by fdtdec_setup() to find the blob.
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Since we don't use gp for small data with option "-G0",
we use gp as global data pointer. The _gp location is
not needed.
The ALIGN(16) was for gp only. It is removed, so that we
can get correct address of dtb in u-boot-dtb.bin image.
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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As we will use u-boot-dtb.bin, the code relocation range
should be adjusted to accommodate the additional dtb.
It might be overkilled to look into dtb header to find the
dtb size, so we will simply use CONFIG_SYS_MONITOR_LEN.
Signed-off-by: Thomas Chou <[email protected]>
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As dtb in u-boot-dtb.bin overlapped the BSS section,
we should delay the clearing of BSS until dtb is relocated
in board_init_f().
Signed-off-by: Thomas Chou <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Enable this in the Kconfig so that nios2 boards can use device
tree to configure U-Boot.
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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