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There is a hole in shadow registers address map of size 0x100
between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
we should account for this hole in address space.
Similar hole exists between bank 14 and bank 15 of size
0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
Note: iMX6SL has only 0-7 banks and there is no hole.
Note: iMX6UL doesn't have this one.
When reading, we use register offset, so need to account for holes
to get the correct address.
When writing, we use bank/word index, there is no need to account
for holes, always use bank/word index from fuse map.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
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there is a 2b board version of the aristainetos2
board. Differences to the v2:
- spi cs for the nor flash and display controller
changed
- some pinmux changes
- LED gpio settings changed
Signed-off-by: Heiko Schocher <[email protected]>
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There is no need to expose SoC choice to user, we already got
the SoC according to the build target. So default "select MX6UL"
for MX6UL_14x14_EVK target.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
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To i.MX6UL, SYS_L2CACHE_OFF is selected, but there is no Kconfig entry
for SYS_L2CACHE_OFF. Then "select SYS_L2CACHE_OFF" does not effect for
i.MX6UL, which is not expected.
Since SYS_L2CACHE_OFF is mainly used by ARM architecture, add it to
arch/arm/Kconfig.
Signed-off-by: Peng Fan <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add SPL boot support for mx6slevk board.
1. Introduce a configuration file mx6slevk_spl_defconfig.
2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE.
3. Include imx6_spl.h and related SPL macro in mx6slevk.h.
4. select SUPPORT_SPL for TARGET_MX6SLEVK.
5. Add SPL board code to do related initialization.
Boot Log:
U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59)
reading u-boot.img
reading u-boot.img
U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000)
CPU: Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C) at 50C
Reset cause: POR
Board: MX6SLEVK
I2C: ready
DRAM: 1 GiB
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
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Add LPDDR2 support:
1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2.
2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to
mx6_ddr3_cfg, but still keep it a single one for easy to choose
parameters for LPDDR2.
3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to init MMDC.
4. Update comments.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
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To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.
Initialize ddr_type for different boards which enable SPL.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Fabio Estevam <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Add ddr_type entry for mx6_ddr_sysinfo. It will be used for
differenrate DDR3 and LPDDR2.
Introduce an enum type for ddr_type.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
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Add mpzqlp2ctl entry for mx6_mmdc_calibration.
MMDC_MPZQLP2CTL register is for init tZQINIT, tZQCL, tZQCS for LPDDR2 chips.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
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Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs.
Add a new function mx6sl_dram_iocfg to configure dram io.
Add header file to define macros for register address.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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To Chip density 4Gb, tRFC should be 300ns, see
"Table 61 — Refresh parameters by device density" of JESD79-3E.
tXS(min) is max(5nCK, tRFC(min) + 10ns).
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Add more register entry for MMDC structure.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Signed-off-by: Soeren Moch <[email protected]>
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* Add mxc_gpio support for imx7d SoC
* Use CONFIG_MX7 to extend mxc gpio driver support for imx7d
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Adrian Alonso <[email protected]>
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* Add imx7d support for iomux controller
* imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr
(0x302C0000) each conroller provides control and mux mode pad
registers but shares iomuxc input select register with iomuxc-lpsr
IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings
for iomuxc-lpsr pads.
* Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3
driver for these LPSR pins.
Signed-off-by: Adrian Alonso <[email protected]>
Signed-off-by: Fugang Duan <[email protected]>
Signed-off-by: Ye.Li <[email protected]>
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To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.
Signed-off-by: Peng Fan <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Nikolaos Pasaloukos <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Move most macro definitions and prototypes into
"arch/arm/include/asm/imx-common/sys_proto.h" to avoid duplicated
function prototypes and marco definitions for different i.MX SoCs.
This patch do not remove the sys_proto.h for different i.MX SoCs,
because we need to modify lots of driver code and others. This patch
remove duplicated macros and prototypes and incude "sys_proto.h"
of imx-common for each sys_proto.h of different i.MX platforms.
Then later we should avoid add stuff in sys_proto.h of each platform,
and modify driver to include common sys_proto.h.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Rewrite get_cpu_rev, from "static const char *get_cpu_rev(void)" to
"u32 get_cpu_rev(void)". To align with get_cpu_rev of other i.MXes.
Also write get_imx_type to replace get_cpu_type, since we have
macro named get_cpu_type.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Use new formula for get_cpu_rev, since we need to use this formula
to do runtime check for all i.MXes.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Implement get_cpu_rev to support runtime check using is_cpu_type.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Add cpu types for i.MX2/3.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Move TARGET_xx Kconfig option based on mx6 to arch/arm/cpu/armv7/mx6/Kconfig.
Add enable "CONFIG_ARCH_MX6" for boards based on mx6.
Then we can choose target boards using "make ARCH=arm menuconfig"
with ARCH_MX6 defined.
If using original way, we have no chance to enable ARCH_MX6 when
"make menuconfig". Even define CONFIG_ARCH_MX6=y in xx_defconfig,
kconfig will complains "arch/../configs/platinum_titanium_defconfig:3:
warning: override: TARGET_PLATINUM_TITANIUM changes choice state"
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Tim Harvey <[email protected]>
Cc: Eric Bénard <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Christian Gmeiner <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Soeren Moch <[email protected]>
Cc: Otavio Salvador <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Acked-by: Soeren Moch <[email protected]>
Acked-by: Otavio Salvador <[email protected]>
Acked-by: Christian Gmeiner <[email protected]>
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This commit adds ethernet support to the TS4800. Note that the
MAC address is not fused on this board and have to be read from
FEC PALR PAUR registers (this is how the kernel provided by
Technologic Systems does it).
signed-off-by: Damien Riegel <[email protected]>
Cc: Stefano Babic <[email protected]>
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This commit adds basic support including:
MMC, Serial console, TS4800 watchdog
The config use CONFIG_SKIP_LOWLEVEL_INIT as U-boot is used as a second
stage bootloader.
Signed-off-by: Lucile Quirion <[email protected]>
signed-off-by: Damien Riegel <[email protected]>
Cc: Stefano Babic <[email protected]>
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Remove this ad-hoc mkimage invocation in MXS Makefile and replace
it with the standard mkimage rule instead.
This patch fixes recent build issues introduced by the patch
92a655c mkimage: Set up a file size parameter and keep it updated
These build issues could be triggered by building for example the
MX28EVK and the u-boot.sb image:
$ make mx28evk_defconfig
$ make V=1 u-boot.sb
[...]
make -f ./scripts/Makefile.build obj=arch/arm/cpu/arm926ejs/mxs u-boot.sb
./tools/mkimage -n arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg -T mxsimage u-boot.sb
./tools/mkimage: Can't open (null): Bad address
arch/arm/cpu/arm926ejs/mxs/Makefile:82: recipe for target 'u-boot.sb' failed
make[1]: *** [u-boot.sb] Error 1
Makefile:989: recipe for target 'u-boot.sb' failed
make: *** [u-boot.sb] Error 2
With this patch:
./tools/mkimage -n arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg -T mxsimage -d arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg u-boot.sb
Signed-off-by: Marek Vasut <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Juha Lumme <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Currently we need to build one U-boot image for each of the udoo
variants: quad and dual-lite.
By switching to SPL we can support all two variants with a single binary.
Based on the SPL for wandboard.
Tested with OpenELEC (Open Embedded Linux Entertainment Center)
on both boards.
Signed-off-by: Peter Vicman <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Signed-off-by: Peter Vicman <[email protected]>
Acked-by: Fabio Estevam <[email protected]>
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This patch rewrites MMU translation table entries. To start, all table
entries are written as "invalid", then "device-ngnrnr" and "normal" are
written to the entries to enable access to specific addresses.
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: York Sun <[email protected]>
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DEVDISRn registers provides a mechanism for gating clocks of IP blocks
that are not used. Here we implement hwconfig option to allow users
to disable unused peripherals on the board.
For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts,
User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma"
in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to
save more power.
Signed-off-by: Zhuoyu Zhang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.
Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil <[email protected]>
Acked-by: Alison Wang <[email protected]>
Tested-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Every QSGMII SerDes Protocol usage 4 MACs.
So add/repeat QSGMII information for 4 MACs in dpmac_info strucuture.
Signed-off-by: King Chung [email protected] <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Update 0x33 and 0x35 serdes protocol as per updated SoC document
in array serdes1_cfg_tbl.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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ISBC Key Extension feature is not applicable for RAMBOOT
as there is no way to retrieve the CSF Header and validated
IE Key table from SRAM once CPC has been disabled.
The feature is only applicable in case of NOR SECURE BOOT.
Code Cleanup:
The SECURE_BOOT specific defines have been moved from
arch-ls102xa/config.h to
arm/include/asm/fsl_secure_boot.h
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch adds a minimal framework for Dickens CCN-504
interconnect configuration - mainly related to adding Clusters/cores
to snoop/DVM domain and setting QoS of the RN-I ports.
LS2085A platform makes use of these configurations to support
better network data performance and to boot a SMP Linux.
Signed-off-by: Bhupesh Sharma <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Recently the FMan Port and MAC compatibles were changed.
This patch aligns the FMan Port and MAC compatibles
to the new FMan device tree binding document.
The FMan device tree binding document can be found in the Linux kernel:
./Documentation/devicetree/bindings/powerpc/fsl/fman.txt
This patch doesn't affect legacy compatibles support.
Signed-off-by: Igal Liberman <[email protected]>
Tested-by: Xing Lei <[email protected]>
Reviewed-by: York Sun <[email protected]>
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MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
through cache on E6500. L2 cache is enabled to to hold the data. This
patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.
Signed-off-by: York Sun <[email protected]>
Reported-by: Jeffery Zhu <[email protected]>
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This driver actually does nothing but test pinctrl uclass, and
demonstrate how things work.
To try this driver, uncomment /* #define DEBUG */ in the
drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be
displayed.
DRAM: 128 MiB
sandbox pinmux: group = 1 (serial_a), function = 1 (serial)
Using default environment
In: cros-ec-keyb
Out: lcd
Err: lcd
Net: Net Initialization Skipped
eth0: eth@10002000, eth1: eth@80000000, eth5: eth@90000000
=> i2c dev 0
Setting bus to 0
sandbox pinmux: group = 0 (i2c), function = 0 (i2c)
sandbox pinconf: group = 0 (i2c), param = 3, arg = 1
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Add a TPM node to the various Chromebooks so that driver can be converted to
driver model.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Christophe Ricard<[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Convert the sandbox TPM driver to use driver model. Add it to the device
tree so that it can be found on start-up.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Christophe Ricard <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Stout is an entry level development board based on R-Car H2 SoC (R8A7790)
This commit supports the following peripherals:
- SCIFA, I2C, Ethernet, QSPI, SDHI0/2, CPLD
Signed-off-by: Vladimir Barinov <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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add SCIFA port base offsets
Signed-off-by: Vladimir Barinov <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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On the A31s the RTC is by default secured. Thus when u-boot
loads the kernel in non-secure world, the RTC is unavailable. The
SoC has a TrustZone Protection Controller, which can be used to
enable non-secure access to the RTC.
On the A31 the TZPC doesn't seem to do anything, i.e. changes to
its register contents do not affect access to the RTC.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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Signed-off-by: Marcus Cooper <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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The inet98v_rev2 is a pcb used in generic A13 based tablets. It features
volume buttons, a power barrel, micro-usb otg, headphone connector and
a power button.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The gt90h is a pcb found in generic 9" tablets with an A23 soc, 1G RAM
and 8G nand, rtl8723as usb wifi, 1 micro usb port and 1 micro sd slot.
The pmic setup on this board is somewhat special, dcdc2 MUST be set
to 1.1V instead of the usual 1.2V otherwise the board is very unstable.
aldo1 is used to power the micro sd slot, dldo1 is used for wifi.
This commit adds a defconfig + dts (as submitted to the kernel) for
the gt90h-v4 pcb.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Initial version of DTSI for ProXstream2 and PH1-LD6b and DTS for
PH1-LD6b reference board.
Import from Linux with some adjustments:
- Use SPDX-License-Identifier
- Add clock-frequency to serial nodes
- Drop unusable nodes from -ref.dts
While I am here, sort Makefile entries alphabetically.
Signed-off-by: Masahiro Yamada <[email protected]>
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Initial version of UniPhier PH1-Pro5 device tree.
(Imported from Linux with adjustment for SPDX License Identifier)
Signed-off-by: Masahiro Yamada <[email protected]>
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This commit imports device tree updates from Linux. It eventually
adds pinctrl-related nodes and properties.
Signed-off-by: Masahiro Yamada <[email protected]>
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Device Tree really improves code maintainability and is now
available for SPL too.
This is the state-of-the-art implementation in U-boot.
The board files (platform data) are no longer needed.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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