| Age | Commit message (Collapse) | Author |
|---|
|
These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada <[email protected]>
|
|
These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada <[email protected]>
|
|
These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada <[email protected]>
|
|
These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada <[email protected]>
|
|
* This is done by limiting the ARM's bandwidth and setting DSS priority in
the EMIF controller to ensure underflows do not occur.
|
|
* Boot failures have been discovered due to a combination of routing issues and
non optimal ddr3 timings in the EMIF
* Since ddr3 timings are different after significant board layout changes
different timings are required for alpha, beta and production boards.
Signed-off-by: Franklin S. Cooper Jr <[email protected]>
|
|
The directory arch/${ARCH}/cpu/${CPU} does not exist
in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86.
These architectures have only one CPU type.
Defining CPU should not be required for such architectures.
This commit allows cpu field (= the 3rd field of boards.cfg)
to be kept blank.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Andreas Bießmann <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Sonic Zhang <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Thomas Chou <[email protected]>
Cc: Stefan Kristiansson <[email protected]>
|
|
The code intends for the CM_DLL_READYST to be set, but
actually polls till any bit is set since the logical
AND is used instead of the bitwise one is used. Fix it.
cc: Lokesh Vutla <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
|
|
|
|
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
|
|
Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner
sun5i family, and the A13-OLinuXinoM A13 based and r7-tv-dongle A10s based
boards.
The only differences compared to the already supported sun4i and sun7i
families are all in the DRAM controller initialization:
-Different hcpr values
-Different MBUS settings
-Some other small initialization changes
Signed-off-by: Henrik Nordstrom <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
|
|
Add support for the Allwinner A10 SoC also known as the Allwinner sun4i family,
and add the Cubieboard board which uses the A10 SoC.
Compared to sun7 only the DRAM controller is a bit different:
-Controller reset bits are inverted, but only for Rev. A
-Different hpcr values
-No MBUS on sun4i
-Various other initialization changes
Signed-off-by: Henrik Nordstrom <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
|
|
There is no way to reset the cpu, so use the watchdog for this.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
|
|
Adjust the u-boot-spl.lds linker script to match the changes made in the
41623c91b09a0c865fab41acdaff30f060f29ad6 "arm: move exception handling out
of start.S files" commit.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
|
|
To move the arch common function away from board folder to
arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication
for other non Altera dev kit which is using socfpga device.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Detlev Zundel <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Acked-by: Detlev Zundel <[email protected]>
|
|
Fix following compilation error when CONFIG_ARM64 is defined
Error: unknown or missing system register name at operand 2
-- `mrs x0,daifmsr daifset,#3'
Signed-off-by: Shaibal.Dutta <[email protected]>
Signed-off-by: Darwin Rambo <[email protected]>
Reviewed-by: Darwin Rambo <[email protected]>
|
|
cc: Tom Rini <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
|
|
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Wolfgang Denk <[email protected]>
CC: Pavel Machek <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
|
|
To enable the DesignWare watchdog support at SOCFPGA
Cyclone V dev kit.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Tom Rini <[email protected]>
|
|
This patch returns back support for old ep93xx processors family
Signed-off-by: Sergey Kostanbaev <[email protected]>
Cc: [email protected]
|
|
This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.
cc: Albert Aribaud <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Support for GIC 500 (based on GICv3 arch)
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Arnab Basu <[email protected]>
Signed-off-by: J. German Rivera <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
|
|
Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.
Signed-off-by: J. German Rivera <[email protected]>
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Lijun Pan <[email protected]>
Signed-off-by: Shruti Kanetkar <[email protected]>
|
|
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Varun Sethi <[email protected]>
Signed-off-by: Arnab Basu <[email protected]>
|
|
Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun <[email protected]>
CC: David Feng <[email protected]>
|
|
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera <[email protected]>
|
|
The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF
images and u-boot, and does this for virtual platforms by using
semihosting. This commit extends this idea by allowing u-boot to also
use semihosting to load the kernel/ramdisk/dtb. This eliminates the need
for a bootwrapper and produces a more realistic boot sequence with
virtual models.
Though the semihosting code is quite generic, support for armv7 in
fastmodel is less useful due to the wide range of available silicon
and the lack of a free armv7 fastmodel, so this change contains an
untested armv7 placeholder for the service trap opcode.
Please refer to doc/README.semihosting for a more detailed description
of semihosting and how it is used with the armv8 virtual platforms.
Signed-off-by: Darwin Rambo <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
|
|
I2C read transactions are typically implemented as follows:
START(write) address REPEATED_START(read) data... STOP
However, Tegra's I2C driver currently implements reads as follows:
START(write) address STOP START(read) data... STOP
This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Yen Lin <[email protected]>
|
|
Conflicts:
boards.cfg
Conflict was trivial between goni maintainer change and
lager_nor removal.
|
|
|
|
|
|
|
|
commit 67a04ab3ab8522a3a34491853e46105317580df5
fix the build for MX25. The same error
happens for VF610 SOC.
Signed-off-by: Stefano Babic <[email protected]>
|
|
|
|
|
|
local_irq_save() should be a macro, not a function
because local_irq_save() saves flag to the given argument.
GCC is silent about this issue, but Clang warns:
In file included from lib/asm-offsets.c:15:
In file included from include/common.h:20:
In file included from include/linux/bitops.h:110:
arch/sandbox/include/asm/bitops.h:59:17:
warning: variable 'flags' is uninitialized when used here
[-Wuninitialized]
local_irq_save(flags);
^~~~~
That change causes another warning:
In file included from include/linux/bitops.h:110:0,
from include/common.h:20,
from lib/asm-offsets.c:15:
arch/sandbox/include/asm/bitops.h: In function ‘test_and_set_bit’:
arch/sandbox/include/asm/bitops.h:56:16: warning: unused variable ‘flags’ [-Wunused-variable]
So, flags should be set to __always_unused.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Jeroen Hofstee <[email protected]>
Acked-by: Simon Glass <[email protected]>
Acked-by: Jeroen Hofstee <[email protected]>
|
|
Each node in the linked-list that os_dirent_ls() returns has its next
pointer set only when the next node is created. For the last node in the
list, there is no next node, so this never happens, and the next pointer
is never initialized. Explicitly initialize the next pointer so that it
isn't dangling. Without this, "sb ls" might crash.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Until now building the x86 arch boards required 32-bit toolchain. As
many x86_64 toolchains come with 32-bit support (multilib) that's a
good idea to enable build with such toolchains.
The change required was to specify the usage of 32-bit explicitly to
the compiler and the linker (-m32 and -m elf_i386 flags) and locate
the right libgcc path.
Signed-off-by: Vasili Galka <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
While the Exynos5420 chip is used in both Smdk5420 and in the Peach-Pit
line of devices, there could be other boards using the same chip, so a
common configuration file is being added (exynos5420.h) as well
as two common device tree files (exynos54xx.dtsi & exynos5420.dtsi).
The peach board as declared in boards.cfg is a copy of smdk5420
declaration. The configuration files are similar, but define different
default device trees, console serial ports and prompts.
The device tree files for smdk5420 and peach-pit inherit from the same
common file.
Signed-off-by: Vadim Bendebury <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Macros defined in exynos5_setup.h specific to SMDK5420
are required for Peach-Pit too. Hence, replacing
CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these
macros for all the boards based on Exynos5420.
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
These files are taken from Linux 3.14.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
|
|
Linux supports this, and if we are to have compatible device tree files,
U-Boot should also.
Avoid giving the device tree files access to U-Boot's include/ directory.
Only include/dt-bindings is accessible.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
|
|
Support the iotrace feature for sandbox, and enable it, using some dummy
I/O access methods.
Signed-off-by: Simon Glass <[email protected]>
|
|
Support the iotrace feature for ARM, when enabled.
Signed-off-by: Simon Glass <[email protected]>
|
|
gpmc timeout is disabled and the reset counter
is set to 0. However, if later a driver activates
the timeout setting the reset to a valid value,
the old reset value with zero is still valid
for the first access. In fact, the timeout block
loads the reset counter after a successful access.
Found on a am335x board with a FPGA connected
to the GPMC bus together with the NAND.
When the FPGA driver in kernel activates
the timeout, the system hangs at the first access
by the NAND driver.
Signed-off-by: Stefano Babic <[email protected]>
|
|
Signed-off-by: Jeroen Hofstee <[email protected]>
|
|
Signed-off-by: Felipe Balbi <[email protected]>
|
|
Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF
definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h
Acked-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
|
|
The definitions inside emif_defs.h concern davinci nand driver and
should be in it's header. So create header file for davinci nand
driver and move definitions from emif_defs.h and nand_defs.h to it.
Acked-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
[trini: Fixup more davinci breakage]
Signed-off-by: Tom Rini <[email protected]>
|
|
If CONFIG_(NAND|NOR|ONENAND) is not defined, no configuration is set
for GPMC on chip select #0---size is 0. In this case, the GPMC
configuration should be reset but not enabled. Enabling causes the
Gumstix DuoVero board to hang when entering Linux.
Signed-off-by: Ash Charles <[email protected]>
[trini: Switch to testing base as GPMC_SIZE_256M is 0x0]
Signed-off-by: Tom Rini <[email protected]>
|
