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FN_SEL_IEB is assigned 2bit, and 2bit can represent 4 patterns.
However FN_SEL_IEB but we only use 3. It adds empty patterns as 0.
Signed-off-by: Hisashi Nakamura <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Fix typo from __ASM_R8A7790_H__ to __ASM_R8A7790_GPIO_H__.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Fix typo from __ASM_R8A7791_H__ to __ASM_R8A7791_GPIO_H__.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Conflicts:
boards.cfg
Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).
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P1020 SoC which has two USB controllers, but only first one is used
on this platform.
Signed-off-by: Ramneek Mehresh <[email protected]>
Reviewed-by: York Sun <[email protected]>
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B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.
Signed-off-by: Shaveta Leekha <[email protected]>
Signed-off-by: Sandeep Singh <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.
Signed-off-by: Minghuan Lian <[email protected]>
Signed-off-by: Chunhe Lan <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Conflicts:
boards.cfg
Trivial conflict, maintainer change plus board addition
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This reverts commit 258060905e04fe2eb509756ef3b37e23e220a2d6.
Conflicts:
boards.cfg
Wrong patch 25806090 was applied by accident. Revert it.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Simon Glass <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Enabled the dw-mmc controller.
Signed-off-by: Jaehoon Chung <[email protected]>
Tested-by: Lukasz Majewski <[email protected]>
Acked-by: Lukasz Majewski <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Exynos serise can be supported the dw-mmc controller.
So, it's good that used the general prefix as "_EXYNOS_DWMMC".
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)
Signed-off-by: Jaehoon Chung <[email protected]>
Tested-by: Lukasz Majewski <[email protected]>
Acked-by: Lukasz Majewski <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch add dwmmc emmc controller node on exynos4 and exynos4412 device tree.
Signed-off-by: Beomho Seo <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
Tested-by: Piotr Wilczek <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Piotr Wilczek <[email protected]>
Cc: Minkyu Kang <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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exynos4x12_set_mmc_clk function have been removed.
Because, exynos4x12_clock and exynos4_clock return same div_fsys* value.
Signed-off-by: Beomho Seo <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
Tested-by: Piotr Wilczek <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Piotr Wilczek <[email protected]>
Cc: Minkyu Kang <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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For use dwmmc controller at exynos4, add SDMMC4 gpio configuration.
Signed-off-by: Beomho Seo <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
Tested-by: Piotr Wilczek <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Piotr Wilczek <[email protected]>
Cc: Minkyu Kang <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Exception handling is basically identical for all ARM targets.
Factorize it out of the various start.S files and into a
single vectors.S file, and adjust linker scripts accordingly.
Signed-off-by: Albert ARIBAUD <[email protected]>
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Signed-off-by: Albert ARIBAUD <[email protected]>
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PXA start.S has a PXA (variant) specific check in
start.S. Move it to cpuinfo.c.
Signed-off-by: Albert ARIBAUD <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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CPUs arm946es and sa1100 both define the reset_cpu()
function in their start.S file. Move this cpu-specific code
into cpu.c so that start.S only contains ARM generic code.
Signed-off-by: Albert ARIBAUD <[email protected]>
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arch/arm/cpu/arm1136/start.S contain a cache flushing function.
Remove the function and move its code into arch/arm/lib/cache.c.
Signed-off-by: Albert ARIBAUD <[email protected]>
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Commit c9416b92 added OF UART initialization support
but aliases nodes are missing in device tree.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Michal Simek <[email protected]>
Tested-by: Masahiro Yamada <[email protected]> [on ZC706 board]
Tested-by: Michal Simek <[email protected]> [on ZC702 board]
Signed-off-by: Michal Simek <[email protected]>
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Commit 9e0e37ac added OF RAM initialization support
but memory nodes are missing in device tree.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Michal Simek <[email protected]>
Tested-by: Masahiro Yamada <[email protected]> [on ZC706 board]
Tested-by: Michal Simek <[email protected]> [on ZC702 board]
Signed-off-by: Michal Simek <[email protected]>
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Our current motivation is to use OF initialization for RAM and UART.
But adding full DTS would be helpful in future, for instance,
for OF configuration of Ethernet, MMC, USB, etc.
This commit imports arch/arm/boot/dts/zynq-7000.dtsi from Linux 3.15-rc5
and adjusts the license comment block for SPDX.
Signed-off-by: Masahiro Yamada <[email protected]>
Suggested-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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A few changes are made to the Tegra EHCI driver so that it can set
everything up for device-mode operation on the first USB controller.
This can be used in conjunction with ci_udc.c to operate as a USB
device.
Detailed changes are:
* Rename set_host_mode() to set_up_vbus() since that's really what it
does.
* Modify set_up_vbus() to know whether it's initializing in host or
device mode, and:
- Skip the external VBUS check in device mode, since external VBUS is
expected in this case.
- Disable VBUS output in device mode.
* Modify init_phy_mux() to know whether it's initializing in host or
device mode, and hence skip setting USBMODE_CM_HC (which enables host
mode) in device mode. See the comments in that function for why this
is safe w.r.t. the ordering requirements of PHY selection.
* Modify init_utmi_usb_controller() to force "b session valid" in device
mode, since the HW requires this. This is done in UTMI-specific code,
since we only support device mode on the first USB controller, and that
controller can only talk to a UTMI PHY.
* Enhance ehci_hcd_init() to error-check the requested host-/device-mode
vs. the dr_mode (dual-role mode) value present in device tree, and the
HW configurations which support device mode.
* Enhance ehci_hcd_init() not to skip HW initialization when switching
between host and device mode on a controller. This requires remembering
which mode the last initialization used.
Cc: Jim Lin <[email protected]>
Cc: Stefan Agner <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
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ps7_init.c and ps7_init.h are supposed to be exported by hw project
and copied to board/xilinx/zynq/ directory.
We want them to be ignored by git.
So what we should do is to always treat them as external files
rather than replacing ps7_init.c
This commit does:
- Move a weak function ps7_init() to arch/arm/cpu/armv7/zynq/spl.c
and delete board/xilinx/zynq/ps7_init.c
- Compile board/xilinx/zynq/ps7_init.c only when it exists
- Add .gitignore to ignore ps7_init.c/h
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Added USB host driver for zynq.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add run-time MIO pin detection to get actual
pin configuration for specific periphery.
Signed-off-by: Michal Simek <[email protected]>
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Bootmode mask was defined as 0x0F, but documentation mentions 0x07.
Experiments show that bit "3" is the JTAG chain configuration.
Change the mask to "7" to allow systems with a different chain
configuration to boot correctly.
Signed-off-by: Mike Looijmans <[email protected]>
Acked-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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The driver should setup slcr state according
to slcr operations.
Reported-by: Andrey Filippov <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Fix c&p error in zynq_slcr_devcfg_enable() commentary
and extending it with description according
to Zynq TRM also in zynq_slcr_devcfg_disable().
Signed-off-by: Michal Simek <[email protected]>
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Call board_init() if SPL is configured with CONFIG_SPL_BOARD_INIT.
Signed-off-by: Michal Simek <[email protected]>
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Memory size should be specified without ECC place.
If you need to have half memory size, please change
u-boot configuration.
Signed-off-by: Michal Simek <[email protected]>
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Added efuse status register base address. This register
is used for determining whether efuse was blown or not.
Also, added the zynq_get_silicon_version() to get the
silicon version of the zynq board.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Warning:
arch/arm/cpu/armv7/zynq/ddrc.c:43:24: warning: Using plain integer as NULL pointer
Signed-off-by: Michal Simek <[email protected]>
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Warnings:
arch/arm/cpu/armv7/zynq/slcr.c:21:6: warning: symbol 'zynq_slcr_lock' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:27:6: warning: symbol 'zynq_slcr_unlock' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:34:6: warning: symbol 'zynq_slcr_cpu_reset' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:54:6: warning: symbol 'zynq_slcr_gem_clk_setup' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:81:6: warning: symbol 'zynq_slcr_devcfg_disable' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:94:6: warning: symbol 'zynq_slcr_devcfg_enable' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:107:5: warning: symbol 'zynq_slcr_get_boot_mode' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:113:5: warning: symbol 'zynq_slcr_get_idcode' was not declared. Should it be static?
Signed-off-by: Michal Simek <[email protected]>
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Add CKOBUFFER_CLK_EN bit mask enabling FREF_XTAL_CLK clock.
Signed-off-by: Dmitry Lifshitz <[email protected]>
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Add UART4 base address.
Signed-off-by: Dmitry Lifshitz <[email protected]>
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Signed-off-by: Yegor Yefremov <[email protected]>
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U-Boot on Tegra30 currently selects a main CPU frequency that cannot be
supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values
on some others. This can result in unreliable operation of the main CPUs.
Resolve this by switching to a CPU frequency that can be supported by any
SKU. According to the following link, the maximum supported CPU frequency
of the slowest Tegra30 SKU is 600MHz:
repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary
branch l4t/l4t-r16-r2
path arch/arm/mach-tegra/tegra3_dvfs.c
table cpu_dvfs_table[]
According to that same table, the minimum VDD_CPU required to operate at
that frequency across all SKUs is 1.007V. Given the adjustment resolution
of the TPS65911 PMIC that's used on all Tegra30-based boards we support,
we'll end up using 1.0125V instead.
At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates
that VDD_CORE must be at least 1.2V on all SKUs. According to
tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree),
that voltage is safe for all SKUs.
An alternative would be to port much of the code from tegra3_dvfs.c and
tegra3_speedo.c in the kernel tree mentioned above. That's more work
than I want to take on right now.
While all the currently supported boards use the same regulator chip for
VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we
add some small conditional code to select how VDD_CORE is programmed. If
this becomes more complex in the future as new boards are added, or we
end up adding code to detect the SoC SKU and dynamically determine the
allowed frequency and required voltages, we should probably make this a
runtime call into a function provided by the board file and/or relevant
PMIC driver.
Cc: Alban Bedel <[email protected]>
Cc: Marcel Ziswiler <[email protected]>
Cc: Bard Liao <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Add a function to the pinmux driver to allow boards to do this.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The HW-defined procedure for booting Tegra requires that some pins be
set up as GPIOs immediately at boot in order to avoid glitches on those
pins, when the pinmux is programmed. Add a feature to the GPIO driver
which executes a GPIO configuration table. Board files will use this to
implement the correct HW initialization procedure.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed
to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change
the mux option in HW.
For pins that will be used as GPIOs, the mux option is irrelevant, so we
simply don't want to define any mux option in the pinmux initialization
table.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The register writes performed by arch/arm/cpu/arm720t/tegra30/cpu.c
enable_cpu_power_rail() set the voltage to 1.0V not 1.4V as the comment
implies. Fix the comment.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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