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Before parsing LAW table i.e. init_law, boot loader should disable all
previous LAWs except DDR LAWs which has been created by previous
pre boot loader during DDR initialization.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Current SPL code base has BSS section placed after reset_vector. This means
they have to relocate to use the global variables. This put an implicit
requirement of having SPL size = Memory/2.
To avoid relocation:
- Move bss_section within SPL range
- Modify relocate_code()
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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SPL linker has fix location of bootpg and reset vector with respect to text base.
It is not necessary to have fixed locations.
Avoid such hardcoding.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.
So LAW_EN define outside of configs
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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qe_init() does not use data copied from NAND. Thise code is not tested or
complied causing compilation error during NAND boot
So, remove QE firmware copy from NAND to ddr.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.
Signed-off-by: Tang Yuantian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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T1040RDB and T1040QDS boards have an integrated l2 switch.
The switch needs a MAC address for Layer 2 protocols
(MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add
a MAC in device-tree, under node l2switch.
Signed-off-by: Codrin Ciubotariu <[email protected]>
Cc: York Sun <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Erratum A007212 for DDR is about a runaway condition for DDR PLL
oscilliator. Please refer to erratum document for detail.
For this workaround to work, DDR PLL needs to be disabled in RCW.
However, u-boot needs to know the expected PLL ratio. We put the
ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
if DDR PLL ratio is set, or the reserved field is not set.
Workaround for erratum A007212 applies to selected versions of
B4/T4 SoCs. It is safe to apply the workaround to all versions. It
is helpful for upgrading SoC without changing u-boot. In case DDR
PLL is disabled by RCW (part of the erratum workaround), we need this
u-boot workround to bring up DDR clock.
Signed-off-by: York Sun <[email protected]>
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Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
P1010 rev 1.0
B4860 rev 1.0, 2.0
P4080 rev 2.0, 3.0
Signed-off-by: Nikhil Badola <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.
Signed-off-by: York Sun <[email protected]>
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The value written to L2CSR1 didn't match the value written to the
device tree.
Signed-off-by: Scott Wood <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Modify code to adapt to both u-qe and qe.
U_QE is a kind of cutted QE.
the differences between U_QE and QE
1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
2. IMMR: have different immr base addr.
3. iopin: U_QE doesn't need to config iopin.
Signed-off-by: Zhao Qiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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CONFIG_SYS_QE_FW_ADDR
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Secure Boot Target is added for T1040QDS and T1040RDB
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and
CONFIG_T1040RDB
Signed-off-by: Gaurav Rana <[email protected]>
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Secure Boot Target is added for T2080QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS.
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Secure Boot Target is added for T4240QDS and T4160QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS.
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.
Signed-off-by: Ruchika Gupta <[email protected]>
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add NOR, SPI and SD secure boot targets for BSC9132QDS.
Changes:
- Debug TLB entry is not required for Secure Boot Target.
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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ISBC creates a LAW 0 entry for non PBL platforms, which is not
disabled before transferring the control to uboot.
The LAW 0 entry has to be disabled.
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.
It also provides more PCI slots and is supposed to be enumerated by
device tree only.
This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.
Signed-off-by: Alexander Graf <[email protected]>
Acked-by: Scott Wood <[email protected]>
Reviewed-by: York Sun <[email protected]>
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We want to be able to directly execute the ELF binary without going
through the u-boot.bin one.
To know where we have to start executing this ELF binary we have to
tell the linker where our entry point is.
Signed-off-by: Alexander Graf <[email protected]>
Acked-by: Scott Wood <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The DDR mapping function really is just a generic virtual -> physical
mapping function. Generalize it so it can support any virtual starting
offset and IO maps just the same.
Signed-off-by: Alexander Graf <[email protected]>
Acked-by: Scott Wood <[email protected]>
Reviewed-by: York Sun <[email protected]>
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There is no need to set IVORs to anything but their default values,
so let's leave them where they are.
Suggested-by: Scott Wood <[email protected]>
Signed-off-by: Alexander Graf <[email protected]>
Acked-by: Scott Wood <[email protected]>
[York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile]
Reviewed-by: York Sun <[email protected]>
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This is dead hardware and no one is interested in making the
necessary changes for upcoming features like generic board or
driver model.
Signed-off-by: Daniel Schwierzeck <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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This patch allows MIPS boards to make use of generic board, replacing
arch/mips/lib/board.c with common/board_{f,r}.c and struct bd_info with
the asm-generic version.
Signed-off-by: Paul Burton <[email protected]>
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The generic board code uses the __init_end symbol to calculate
monitor_flash_len. Define said symbol for MIPS, equivalent to
__image_copy_end which is used for the same purpose in
arch/mips/lib/board.c.
Signed-off-by: Paul Burton <[email protected]>
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Move the definition of this variable out of arch/mips/lib/board.c in
preparation for allowing use of generic board on MIPS, which will lead
to this file not being compiled.
Signed-off-by: Paul Burton <[email protected]>
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interrupt_init is called unconditionally by the generic board code.
Define a stub for it on MIPS like the enable & disable functions.
Signed-off-by: Paul Burton <[email protected]>
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Commit 54e458de deleted qi_lb60 board support
because of the incompatible license issue.
There is no board with XBurst CPU.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
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Always keep all sections in u-boot ELF binary. Move all unneeded
sections after _end to avoid allocating space in the final binary.
Also remove .deadcode section which is now obsolete.
Signed-off-by: Daniel Schwierzeck <[email protected]>
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In 6e7b9f4 some of the debug prints for AES code moved into the generic
code, so we remove these additional calls.
Signed-off-by: Tom Rini <[email protected]>
Acked-by: Tom Warren <[email protected]>
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Tegra's crypto.c uses apply_cbc_chain_data() to sign the warm restart
code. This function was recently moved into the core aes.c and made
static, which prevents the Tegra code from compiling. Make it public
again to avoid the compile errors:
arch/arm/cpu/tegra20-common/crypto.c: In function ‘sign_object’:
arch/arm/cpu/tegra20-common/crypto.c:74:3: warning: implicit declaration of function ‘apply_cbc_chain_data’ [-Wimplicit-function-declaration]
arch/arm/cpu/built-in.o: In function `sign_object':
.../arch/arm/cpu/tegra20-common/crypto.c:74: undefined reference to `apply_cbc_chain_data'
.../arch/arm/cpu/tegra20-common/crypto.c:78: undefined reference to `apply_cbc_chain_data'
Fixes: 6e7b9f4fa0ae ("aes: Move the AES-128-CBC encryption function to common code")
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/mousse/*
- Remove include/configs/MOUSSE.h
- Clean-up defined(CONFIG_MOUSSE)
- Move the entry from boards.cfg to doc/README.scrapyard
Signed-off-by: Masahiro Yamada <[email protected]>
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Enough time has passed since these boards were moved to Orphan. Remove.
- Remove board/RPXlite/*
- Remove board/RPXClassic/*
- Remove include/configs/RPXlite.h
- Remove include/configs/RPXClassic.h
- Clean-up defined(CONFIG_RPXCLASSIC)
- Move the entry from boards.cfg to doc/README.scrapyard
Signed-off-by: Masahiro Yamada <[email protected]>
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Enough time has passed since these boards were moved to Orphan. Remove.
- Remove include/configs/{ADS860.h,FADS823.h,FADS850SAR.h,FADS860T.h}
- Cleanup defined(CONFIG_ADS), defined(CONFIG_MPC823FADS),
defined(CONFIG_MPC850SAR), defined(CONFIG_SYS_DAUGHTERBOARD)
- Remove the entries from boards.cfg
Signed-off-by: Masahiro Yamada <[email protected]>
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Enough time has passed since these boards were moved to Orphan. Remove.
- Remove board/mbx8xx/*
- Remove include/configs/{MBX.h,MBX860T.h}
- Clean-up if defined(CONFIG_MBX)
- Move the entries from boards.cfg to doc/README.scrapyard
Signed-off-by: Masahiro Yamada <[email protected]>
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Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/nx823/*
- Remove include/configs/NX823.h
- Clean-up ifdef(CONFIG_NX823)
- Move the entry from boards.cfg to doc/README.scrapyard
Signed-off-by: Masahiro Yamada <[email protected]>
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This required moving it into a C file from the header.
The only user of a non-default name_to_gpio is blackfin, therefore build tested
with the blackfin bct-brettl2 build, which is one I picked at random. Also
tested with a build for the ARM tec board which uses the default/fallback
implementation. Inspection with objdump shows that both have done the right
thing.
This change was requested by Marek during review of the sunxi patch series.
Signed-off-by: Ian Campbell <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Sonic Zhang <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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References to the wireless keyboard should also be removed
from README.console.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Acked-by: Wolfgang Denk <[email protected]>
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Make funtions static which are locally used in file
and remove the declaration from header file.
Signed-off-by: Manish Badarkhe <[email protected]>
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In the case of SPL or NOR_BOOT (no SPL involved) we need to include
certain code in the build. Use !CONFIG_SKIP_LOWLEVEL_INIT rather than
CONFIG_SPL_BUILD || CONFIG_NOR_BOOT to make the code clearer, and to
make supporting XIP QSPI boot clearer in the code.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Wolfgang Denk <[email protected]>
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Ethernet driver configures the CPSW, SGMI and Phy and uses
the the Navigator APIs. The driver supports 4 Ethernet ports and
can work with only one port at a time.
Port configurations are defined in board.c.
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
Signed-off-by: WingMan Kwok <[email protected]>
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Multicore navigator consists of Network Coprocessor (NetCP) and
Queue Manager sub system. More details on the hardware can
be obtained from the following links:-
Network Coprocessor: http://www.ti.com/lit/pdf/sprugz6
Multicore Navigator: http://www.ti.com/lit/pdf/sprugr9
Multicore navigator driver implements APIs to configure
the Queue Manager and NetCP Pkt DMA.
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
Signed-off-by: WingMan Kwok <[email protected]>
Acked-by: Tom Rini <[email protected]>
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k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler
SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please
refer the ti/k2hk_evm/README for details on the board, build and other
information.
This patch add support for keystone architecture and k2hk evm.
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
Signed-off-by: WingMan Kwok <[email protected]>
Signed-off-by: Sandeep Nair <[email protected]>
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- add davinci driver to new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
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This patch moves the davinci i2c_defs.h file to drivers.i2c directory.
It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs.
Not used "git mv" command to move the file because small part of
it with definitions specific for Davinci SOCs has to remain in the
arch/arm/include/asm/arch-davinci.
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
Acked-by: Tom Rini <[email protected]>
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This patch add basic support for the architecture timer found on recent
ARMv7 based SoCs.
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
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