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The RK35xx SoCs contain a crypto engine block that can generate random
numbers.
Enable rng node in soc u-boot.dtsi and enable Kconfig options to take
advantage of the random generator.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Dragan Simic <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Sort imply statements under ROCKCHIP_RK3568 and ROCKCHIP_RK3588
alphabetically.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Dragan Simic <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Move cru_rk3308.h and grf_rk3308.h to arch-rockchip to match path used
for all other Rockchip SoCs.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Update defconfig for rk3308-rock-pi-s with new defaults.
Add OF_LIBFDT_OVERLAY=y to support device tree overlays.
Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.
Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to
allow use of U-Boot cmdline.
Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to
allow full use of USB 2.0 host and otg ports.
Enable EFI_LOADER to allow EFI boot.
Also fix use of USB 2.0 otg port by removing improper use of phy-supply
and regulator-always-on props.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Sync device tree from linux v6.8 and rename the rockchip,rk3308-mac
compatible in gmac_rockchip driver to match upstream linux.
Also move rk3308-roc-cc gmac node to u-boot.dtsi to not break features
not enabled in upstream device tree.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support to get and set the SCLK_RTC32K clock rate.
Signed-off-by: Finley Xiao <[email protected]>
[[email protected]: Update commit message]
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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When RK3308 boards run SPL from eMMC and fail to load FIT from eMMC due
to it being missing or checksum validation fails there can be a fallback
to read FIT from SD-card. However, without proper pinctrl configuration
reading FIT from SD-card may fail:
U-Boot SPL 2024.04-rc4 (Mar 16 2024 - 12:36:12 +0000)
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC1
Card did not respond to voltage select! : -110
mmc_init: -95, time 12
spl: mmc init failed with error: -95
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices (err=-6)
### ERROR ### Please RESET the board ###
Fix this by tagging related emmc and sdmmc pinctrl nodes with bootph
props. Also sort and move common nodes shared by all boards to the SoC
u-boot.dtsi.
Imply SPL_PINCTRL and SPL_DM_SEQ_ALIAS to apply correct pinconf before
trying to load FIT from a device.
Move u-boot,spl-boot-order to soc u-boot.dtsi and define both sdmmc and
emmc nodes as fallback.
Also fix boot from eMMC (SD NAND) on ROCK Pi S by using correct pinctrl.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The RK3308 SoC contain a crypto engine block that can generate random
numbers.
Add rng node to soc u-boot.dtsi and enable Kconfig options to take
advantage of the random generator.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Like other Rockchip SoCs the RK3308 has cpu id programmed into OTP
memory. The rockchip_otp driver already support the RK3308 variant.
However, the device tree is missing a node to enable use of OTP.
Add the missing otp node to soc u-boot.dtsi, enable the rockchip_otp
driver and enable use of misc_init_r() to set ethaddr based on cpu id.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The RK3308 SoC support ARMv8 Cryptography Extensions and use of the
ARMv8 crypto extensions help speed up FIT checksum validation in SPL.
Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto
extensions for SHA256 when validating checksum of FIT images.
Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum
validation on all RK3308 boards.
Also disable CONFIG_SPL_RAW_IMAGE_SUPPORT in board defconfigs to ensure
SPL does not try to jump to code that failed checksum validation.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Sort imply statements under ROCKCHIP_RK3308 alphabetically and remove
the config SPL_SERIAL statement from soc Kconfig file, it is already
implyed in arch Kconfig.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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When debugging the SPL boot order, the node ID of a device which hasn't
been found is printed but it can be quite hard to relate that to the
specific devicetree node. To aid debugging, print the node path instead of
the cryptic node ID.
Original debug message:
board_boot_order: could not map node @73c to a boot-device
With this patch applied this becomes e.g:
board_boot_order: could not map node /spi@ff1d0000/flash@0 to a boot-device
Reviewed-by: Dragan Simic <[email protected]>
Signed-off-by: Christopher Obbard <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
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Fix a simple spelling mistake in a comment.
Reviewed-by: Dragan Simic <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Christopher Obbard <[email protected]>
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Add missing boot source id <-> device tree node path mapping for SPI NOR
flash on PX30, RK3288, RK3308, RK3368 and RV1126.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Dragan Simic <[email protected]>
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Rockchip BROM writes a boot source id at CFG_IRAM_BASE + 0x10, this id
indicates from what storage media TPL/SPL was loaded from.
SPL uses this id to determine what device "same-as-spl" represent when
determining from where FIT should be loaded. This works as long as the
boot_devices array contain a matching id <-> node path entry.
However, SPL typically load a small part of TF-A into SRAM and on RK3399
this overwrites the CFG_IRAM_BASE + 0x10 addr used for boot source id.
For affected devices the u-boot,spl-boot-device would not be set when
booting from SPI flash and the flash@0 node was not explicitly listed
in the u-boot,spl-boot-order prop.
Here boot source id is 3 before FIT images is loaded, and 0 after:
U-Boot SPL 2024.04-rc4 (Mar 15 2024 - 17:26:19 +0000)
board_spl_was_booted_from: brom_bootdevice_id 3 maps to '/spi@ff1d0000/flash@0'
Trying to boot from SPI
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256+ OK
## Checking hash(es) for Image u-boot ... sha256+ OK
## Checking hash(es) for Image fdt-1 ... sha256+ OK
## Checking hash(es) for Image atf-2 ... sha256+ OK
## Checking hash(es) for Image atf-3 ... sha256+ OK
board_spl_was_booted_from: failed to resolve brom_bootdevice_id 0
spl_decode_boot_device: could not find udevice for /mmc@fe330000
spl_decode_boot_device: could not find udevice for /mmc@fe320000
spl_perform_fixups: could not map boot_device to ofpath: -19
Use a static brom_bootsource_id_cache to save the boot source id after
an initial read from SRAM to fix this, this allow spl_perform_fixups()
to resolve correct boot source path for "same-as-spl" after SPL have
loaded TF-A related FIT images into memory.
With this the spl-boot-device prop can correctly be resolved to the
SPI flash node in the control FDT:
=> fdt addr ${fdtcontroladdr}
Working FDT set to f1ee6710
=> fdt list /chosen
chosen {
u-boot,spl-boot-device = "/spi@ff1d0000/flash@0";
stdout-path = "serial2:1500000n8";
u-boot,spl-boot-order = "same-as-spl", "/mmc@fe330000", "/mmc@fe320000";
};
Fixes: d57e16c7e712 ("rockchip: find U-boot proper boot device by inverting the logic that sets it")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Dragan Simic <[email protected]>
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Add more bootsource id:
1. BROM_BOOTSOURCE_UNKNOWN
2. BROM_BOOTSOURCE_I2C
3. BROM_BOOTSOURCE_SPI
Signed-off-by: Jason Zhu <[email protected]>
[[email protected]: Update commit message]
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Dragan Simic <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- move to OF_UPSTREAM for sl28
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Use the new device devicetree files in dts/upstream/ and delete the old
ones. Still keep the -u-boot.dtsi with all u-boot specifics around.
There is one catch and that is fsl-ls1028a-kontron-sl28-var3.dts which
is not available upstream (yet!). For now, the base dts is used for this
variant as this only differ in the compatible and the (human readable)
model name.
Signed-off-by: Michael Walle <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Some Qualcomm boards have only one USB controller which is muxed between
the type-c port and an internal USB hub for type-A and ethernet. We
modify the DT for these to force them to host mode in U-Boot. However in
Linux DRD role switching is supported (required, even). Use
ft_board_setup() to adjust the dr_mode property for these boards.
While we're here, define pr_fmt for this file so we can more easily
identify log messages.
Signed-off-by: Caleb Connolly <[email protected]>
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Add a fixup to force dr_mode to host for U-Boot.
Signed-off-by: Caleb Connolly <[email protected]>
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Schneider HMIBSC board dts has already been reviewed upstream on the
linux-arm-msm mailing list. So once it comes through the Linux kernel
release cycle into the U-Boot dts/upstream subtree, a switch to
OF_UPSTREAM can be made. For the time being maintain the U-Boot copy.
Link: https://lore.kernel.org/linux-kernel/[email protected]/
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow
ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is
loaded as a first stage bootloader. It leads to secondary CPUs bringup
failure and later causing the Linux kernel to freeze.
So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's
actually required.
Fixes: 059d526af312 ("mach-snapdragon: generalise board support")
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Pinctrl driver was refactored and moved, but the required header that
it depends on was not included.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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IPQ40xx SoC-s dont have proper SMEM support like more modern Qualcomm
SoC-s so there is no point in selecting the required drivers.
Signed-off-by: Robert Marko <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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These files are all identical (or older) than those in dts/upstream.
Drop them as we now use upstream DTS files with OF_UPSTREAM.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Switch to using upstream DT from dts/upstream.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Qcom SoCs derived boards can come from various OEMs/ODMs and not just
Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly
corressponding to the actual board vendor.
Suggested-by: Stephan Gerhold <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Remove the reference to the xo clock which is on the unsupported rpmhcc
clock controller. It isn't needed for MMC functionality.
Signed-off-by: Caleb Connolly <[email protected]>
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Janne Grunau <[email protected]> says:
This series contains a few misc config changes for Apple silicon
systems:
- switch from the deprecated distro boot scripts to standard boot
- allows EFI console resizing based on the video console size
- enables 16x32 bitmap fonts as Apple devices come with high DPI
displays
- enables 64-bit LBA addressing
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Use standard boot instead of the distro boot scripts. Use
BOOTSTD_FULL instead of BOOTSTD_DEFAULTS for easier interactive use.
Signed-off-by: Janne Grunau <[email protected]>
Reviewed-by: Mark Kettenis <[email protected]>
Reviewed-by: Neal Gompa <[email protected]>
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Michal Simek <[email protected]> says:
I looked as cleaning up some dependencies and I found that qconfig is
reporting some issues. This series is fixing some of them. But there are
still some other pending. That's why please go and fix them if they are
related to your board.
UTF-8: I am using uni2ascii -B < file to do conversion. When you run it in
a loop you will find some other issue with copyright chars or some issues
in files taken from the Linux kernel like DTs. They should be likely fixed
in the kernel first.
Based on discussion I am ignoring names too.
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Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or
names are converted.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Marek Behún <[email protected]>
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Some of Kconfigs are using utf-8 encoding because of used chars. Convert
all of them to ascii enconging. Based on discussion ASCII should be used in
general with the exception of names.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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All errors are generated by ./tools/qconfig.py -b -j8 -i whatever.
Error look like this:
drivers/crypto/Kconfig:9: warning: style: quotes recommended around
'drivers/crypto/nuvoton/Kconfig' in 'source drivers/crypto/nuvoton/Kconfig'
Signed-off-by: Michal Simek <[email protected]>
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Not many and nothing really exciting this time: there are more patches
in fly, but they are not ready yet. I will also send some DT updates
and new board defconfig files later, once they have seen the list. I am
aware of the USB rebasing repo efforts, but would like to see how this
plays out, also we have one compatibility issue that I painstakingly
work around in the U-Boot tree for the last three years or so. So for
now I stick to the previous approach.
So now just some easy changes: support for USB peripheral mode on the
Allwinner F1C100s, T113-s3 SPI boot support, and some SPL cleanup
patches.
The branch passed the gitlab CI run, and brief boot testing on some
boards didn't turn up any issues.
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Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Of all T30 transformers, only the TF700T has a FullHD DSI panel,
which is connected via tc358768 RGB to DSI bridge. Since the
bridge driver is available now, TF700T can have video support.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF700T
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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T20 and T30 have 5 UARTs, while T114+ have only 4. Fix this by
adding missing UARTE Kconfig for T20/T30.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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For lock and io-reset pins 0 is the default value, while 1 is disabled
and 2 is enabled. This should be corrected to avoid regressions.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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TF600T is pretty picky in terms of LV pinmux configuration.
The wrong setup will cause issues with eMMC and video.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Unlike all other transformers, TF600T has an SPI flash to store
boot firmware and requires precise SPI pinmux configuration.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Drop the distro-boot scripts and use standard boot instead.
Inspired by:
'commit 7755dc58af7b ("rockchip: Move to standard boot")'
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Paz00 can have multiple panels with different timings, but they
all share common feature - panel exposes EDID.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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In clock_sun9i.c, responsible for (mostly early) clock setup on the
Allwinner A80 SoC, many functions are only needed by the SPL, and are
thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM, and
they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Move some functions around, to group all SPL-only function within
one #ifdef guard. Some functions were exported, but never used outside
of this file, so remove their prototypes from the header file and mark
them as static.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <[email protected]>
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In clock_sun8i_a83t.c, responsible for (mostly early) clock setup on the
Allwinner A83T SoC, many functions are only needed by the SPL, and are
thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <[email protected]>
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In clock_sun50i_h6.c, responsible for (mostly early) clock setup on
newer generation Allwinner SoCs, many functions are only needed by the
SPL, and are thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only. By moving the clock_get_pll6()
function to the end of the file, all SPL-only clocks can be contained
within one #ifdef guard.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <[email protected]>
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In clock_sun6i.c, responsible for (mostly early) clock setup on older
generation Allwinner SoCs, many functions are only needed by the SPL,
and are thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <[email protected]>
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In clock_sun4i.c, responsible for (mostly early) clock setup on early
generation Allwinner SoCs, many functions are only needed by the SPL,
and are thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <[email protected]>
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With the clock_twi_onoff() function now being called only from the SPL,
the whole clock.c file in arch/arm/mach-sunxi is needed by SPL code
only.
Remove the redundant #ifdef from the clock_init() function, actually
this function was already only called from the SPL.
Then adjust the Makefile to compile clock.c only with CONFIG_SPL_BUILD
defined.
This avoids unnecessary code in U-Boot proper and allows further
refactoring and code-split between the SPL and U-Boot proper.
Signed-off-by: Andre Przywara <[email protected]>
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