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2023-07-21am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.imgNeha Malcom Francis
Support added for HS and GP boot binaries for AM64x. HS-SE: * tiboot3-am64x_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am64x_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am64x-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned Note that the bootflow followed by AM64x requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * sysfw * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * ATF * OP-TEE * A53 SPL * A53 SPL dtbs u-boot.img: * A53 U-Boot * A53 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.imgNeha Malcom Francis
Support has been added for both HS-SE(SR 2.0) and GP(SR 2.0) images. HS-SE: * tiboot3-am65x_sr2-hs-evm.bin * sysfw-am65x_sr2-hs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am65x_sr2-gp-evm.bin * sysfw.itb --> sysfw-am65x_sr2-gp-evm.itb * tispl.bin_unsigned * u-boot.img_unsigned Note that the bootflow followed by AM65x requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * sysfw * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * ATF * OP-TEE * A53 SPL * A53 SPL dtbs u-boot.img: * A53 U-Boot * A53 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.imgNeha Malcom Francis
Support has been added for both HS-SE(SR 2.0), HS-FS(SR 2.0) and GP images. HS-SE: * tiboot3-j7200_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j7200_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-j7200-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J7200 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.imgNeha Malcom Francis
By providing entries in the binman node of the device tree, binman will be able to find and package board config artifacts generated by TIBoardConfig with sysfw.bin and generate the final image sysfw.itb. It will also pick out the R5 SPL and sign it with the help of TI signing entry and generate the final tiboot3.bin. Entries for A72 build have been added to k3-j721e-binman.dtsi to generate tispl.bin and u-boot.img. Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images In HS-SE, the encrypted system firmware binary must be signed along with the signed certificate binary. HS-SE: * tiboot3-j721e_sr1_1-hs-evm.bin * sysfw-j721e_sr1_1-hs-evm.itb * tispl.bin * u-boot.img HS-FS: * tiboot3-j721e_sr2-hs-fs-evm.bin * sysfw-j721e_sr2-hs-fs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin -->tiboot3-j721e-gp-evm.bin * sysfw.itb --> sysfw-j721e-gp-evm.itb * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J721E requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21arm: dts: k3: Add support for packaging sysfw.itb and tiboot3.binNeha Malcom Francis
Board config binary artifacts must be generated to be used by binman to package sysfw.itb and tiboot3.bin for all K3 devices. For devices that follow combined flow, these board configuration binaries must again be packaged into a combined board configuration blobs to be used by binman to package tiboot3.bin. Add common k3-binman.dtsi to generate all the board configuration binaries needed. Also add custMpk.pem and ti-degenerate-key.pem needed for signing GP and HS bootloader images common to all K3 devices. Reviewed-by: Simon Glass <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21board: ti: am62x: evm: Update function calls for splash screenNikhil M Jain
Use spl_dcache_enable, in place of setup_dram, arch_reserve_mmu to set up pagetable, initialise DRAM and enable Dcache to avoid multiple function calls. Check for CONFIG_SPL_VIDEO in place of CONFIG_SPL_VIDEO_TIDSS to prevent any build failure in case video config is not defined and video related functions are called. Check for CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_BMP before calling splash_display to avoid compilation failure. Signed-off-by: Nikhil M Jain <[email protected]>
2023-07-21arch: arm: mach-k3: common: Return a pointer after setting page tableNikhil M Jain
In spl_dcache_enable after setting up page table, set gd->relocaddr pointer to tlb_addr, to get next location to reserve memory. Align tlb_addr with 64KB address. Signed-off-by: Nikhil M Jain <[email protected]> Reviewed-by: Devarsh Thakkar <[email protected]>
2023-07-21arm: mach-k3: am62a7: change some prints to debug printsBryan Brattlof
There is little need to print the devstat information or when we exit a function during a typical boot. Remove them to reduce the noise during typical operation Signed-off-by: Bryan Brattlof <[email protected]>
2023-07-21arm: omap2: Fix warning in force_emif_self_refreshTom Rini
The function declaration for force_emif_self_refresh takes no parameters but does not specify this, only the prototype in the headers do. As clang will warn about this, correct it. Signed-off-by: Tom Rini <[email protected]>
2023-07-21arm: mach-k3: am62: Fixup CPU core, gpu and pru nodes in fdtEmanuele Ghidoli
AM62x SoC is available in multiple variant: - CPU cores (Cortex-A) AM62x1 (1 core), AM62x2 (2 cores), AM62x4 (4 cores) - GPU AM625x with GPU, AM623x without GPU - PRU (Programmable RT unit) can be present or not on AM62x2/AM62x4 Remove the relevant FDT nodes by reading the actual configuration from the SoC registers, with that change is possible to have a single dts/dtb file handling the different variant at runtime. While removing GPU node and CPU nodes also the watchdog node in the same Module Domain is removed. A similar approach is implemented for example on i.MX8 and STM32MP1 SoC. Signed-off-by: Emanuele Ghidoli <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]>
2023-07-21arm: mach-k3: am62: Add CTRLMMR_WKUP_JTAG_DEVICE_ID register definitionEmanuele Ghidoli
Add register address and relevant bitmasks and shifts. Allow reading these information: - device identification - number of cores (part of device identification) - features (currently: PRU / no PRU) - security - functional safety - speed grade - temperature grade - package Signed-off-by: Emanuele Ghidoli <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]> Reviewed-by: Andrew Davis <[email protected]>
2023-07-21arm: k3: Fix ft_system_setup so it can be enabled on any SoCEmanuele Ghidoli
ft_system_setup cannot be enabled on SoC without msmc sram otherwise fdt_fixup_msmc_ram function fails causing system reset. Fix by moving fdt_fixup_msmc_ram to common_fdt.c file and creating SoC (AM654, J721E and J721S2) specific files for fdt fixups. This change was verified to not change anything on any existing board (all the J721S2, AM654 and J721E boards requires it, none of the remaining k3 boards require it). Fixes: 30e96a240156 ("arm: mach-k3: Move MSMC fixup to SoC level") Signed-off-by: Emanuele Ghidoli <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]>
2023-07-21arm: dts: Fix build of am62a7 dtbsNishanth Menon
am62a7 should be built with CONFIG_SOC_K3_AM62A7 not CONFIG_SOC_K3_AM625 Fixes: 6bdfa69155d8 ("arm: dts: introduce am62a7 u-boot dtbs") Cc: Bryan Brattlof <[email protected]> Cc: Vignesh Raghavendra <[email protected]> Cc: Francesco Dolcini <[email protected]> Cc: Sjoerd Simons <[email protected]> Cc: Wadim Egorov <[email protected]> Reviewed-by: Bryan Brattlof <[email protected]> Reviewed-by: Mattijs Korpershoek <[email protected]> Signed-off-by: Nishanth Menon <[email protected]>
2023-07-21arm: mach-k3: *: dev-data: Update to use ARRAY_SIZENishanth Menon
Instead of hard-coding the count of entries manually, use ARRAY_SIZE to keep the count updates appropriately. Cc: Bryan Brattlof <[email protected]> Suggested-by: Ravi Gunasekaran <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Bryan Brattlof <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]>
2023-07-21arm: mach-k3: am62a7_init: Open up FSS_DAT_REG3 firewallVignesh Raghavendra
On security enforced (HS-SE) devices ROM firewalls OSPI data region3 that is present in above 64bit region. Open this up in bootloader to allow Linux to access OSPI flashes in mmap mode. Without this kernel will crash when accessing this region due to firewall violations on HS-SE devices. Signed-off-by: Vignesh Raghavendra <[email protected]>
2023-07-21Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
For once this adds USB support for two SoCs: the H616 and the F1C100s series. The rest is support for LPDDR3 DRAM chips on H616 boards. Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s board. I don't have an H616 board with LPDDR3 DRAM, but reportedly that works for Mikhail, and doesn't regress on my DDR3 boards.
2023-07-21Merge tag 'xilinx-for-v2023.10-rc1-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.10-rc1 v2 axi_emac: - Change return value if RX packet is not ready cadence_qspi: - Enable flash reset for Versal NET dt: - Various DT syncups with Linux kernel - SOM - reserved pmufw memory location fpga: - Add load event mtd: - Add missing dependency for FLASH_CFI_MTD spi/nand: - Minor cleanup in Xilinx drivers versal-net: - Prioritize boot device in boot_targets - Wire mini ospi/qspi/emmc configurations watchdog: - Use new versal-wwdt property xilinx: - fix sparse warnings in various places ps7_init* - add missing headers - consolidate code around zynqmp_mmio_read/write - switch to amd.com email zynqmp_clk: - Add handling for gem rx/tsu clocks zynq_gem: - Configure mdio clock at run time zynq: - Enable fdt overlay support zynq_sdhci: - Call dll reset only for ZynqMP SOCs
2023-07-21arm64: zynqmp: Remove clock-names from pcap nodeMichal Simek
Clock is not used in driver and also not described in binding. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/0a0fa0ba197fa4051a2c8a24e1451cefadce7517.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Rename ams_ps/pl node namesMichal Simek
Fix child node names to be aligned with dt-binding available in the Linux kernel which requires names as ams-ps@ and ams-pl@. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/8f1451d614f654cb0d0da1e799e876c078fbf2c9.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Remove interrupt/reg-names for AMSMichal Simek
These two properties are not described in DT binding and also not used by driver that's why remove them. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/b123c7e537dcf70802e828bbcd484a761a264186.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: remove snps, enable_guctl1_resume_quirk quirk for usbPiyush Mehta
To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk' quirk for usb. This quirk is no more available in linux after the xilinx release 2022.2. This functionality is taken care of by the 'snps,resume-hs-terminations' quirk. Signed-off-by: Piyush Mehta <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/4b7a132116bf0248cdb558e04de3b06b412c4a0f.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: add pmu interrupt-affinityRadhey Shyam Pandey
Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot: armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing. Reported-by: John Toomey <[email protected]> Signed-off-by: Radhey Shyam Pandey <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c2f55a10cf54c6004f5dfe2ea18bcb4cf04f5723.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Sync node name address with reg (mailbox)Michal Simek
Address in node name should match with the first reg property in DT. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/47bea10bbc3c88727c1fe839ff20e15a0c79c339.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Add L2 cache nodesRadhey Shyam Pandey
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it. Reported-by: John Toomey <[email protected]> Signed-off-by: Radhey Shyam Pandey <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Fix usb reset over bootmode pins on zcu100Michal Simek
The commit a4180c369607 ("arm64: zynqmp: Add mode-pin GPIO controller DT node") added usb phy reset over bootmode pins by default on usb0 only. zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744 hub which is used only in host mode. Especially this chip requires reset to operate properly that's why better assign gpio reset to usb1 instead of usb0. Without this change usb start crashed when runs. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/1ca80ec5bf7a595c03822f3e4e3683298205067a.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Cover K24 revB/1 SOMMichal Simek
Extend compatible versions for K24 SOM. Changes are not affecting SW behavior that's why all versions are compatible to each other. Describing all revisions is done by purpose because user space SW is reading compatible string for logic around DT overlays and bitstreams. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/92eba01ac316e58bd2d3508b0e63bbfafbedbb73.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Record compatible string for kv260 rev2Michal Simek
PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335 autofocus feature). PS side is completely unchanged. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/42f78dee8429eeac016d73de5c73af46fdaf4a98.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Assign TSU clock frequency for KV and KD boardsHarini Katakam
Set TSU clock frequency as 250MHz (minimum when running at 1G) on KV and KD carrier cards to allow PTP functionality. Signed-off-by: Harini Katakam <[email protected]> Reviewed-by: Radhey Shyam Pandey <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/4b758d503ef545e4d25d3930b0eb0793f1c415d2.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Increase reset assert time for TI SGMII PHYHarini Katakam
Increase reset assert time for TI SGMII PHY on KR260 CC starting 6.1 kernel. This PHY does not come out of reset with the existing 100us pulse width as per testing on multiple carrier cards. The reset is driven via a PCA9570 I2C expander. The expander driver was updated to an upstream version in 6.1 where gpio_chip _set was optimized. Delays in earlier kernels may have masked this issue. This is a safe workaround value for assert pulse width before the discussions are resolved with TI. Signed-off-by: Harini Katakam <[email protected]> Reviewed-by: Radhey Shyam Pandey <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/8fb9f17d43a43ef504c9f29006cd686cce8ac98b.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Fix gpio comment about No of gpiosMichal Simek
There are total 174 gpios but from 0 - 173 that's why fix comment to reflect it. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c7e94b334e7dd6297e0d3a36a6a3d04bd7e9e967.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Assign TSU clock frequency for KR260Harini Katakam
Set TSU clock frequency as 250MHz (minimum when running at 1G) on KR260 CC to allow PTP functionality. Signed-off-by: Harini Katakam <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Update MALI 400 interrupt and clock namesParth Gajjar
Motivation for the commit is to utilize the upstream community device tree so that the either modified ARM Mali 400 driver or upstream lima driver can be used. Signed-off-by: Parth Gajjar <[email protected]> Signed-off-by: Vishal Sagar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/89d046a9da5638e8b4918f80f3245d73ea46f99f.1688992653.git.michal.simek@amd.com
2023-07-21xilinx: dts: Fix open drain warning on Zynq, ZynqMP and VersalManikanta Guntupalli
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by Linux. "enforced open drain please flag it properly in DT/ACPI DSDT/board file." Signed-off-by: Manikanta Guntupalli <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/056b6f60f89fa2addb762669b80640cd5b31b001.1688992653.git.michal.simek@amd.com
2023-07-21arm: xilinx: Setting default i2c clock frequency to 400kHzVaralaxmi Bingi
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/fb46fe911a68b79c8e4d150ca90c4e94eb5fb9e1.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Switch to amd.com emailsMichal Simek
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-21xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.hMichal Simek
zynqmp_mmio_read/write() are firmware provided hooks that's why use only zynqmp_firmware.h for function declaration. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/e7489556f9e447c737a578c169d7e1e43586a273.1687524706.git.michal.simek@amd.com
2023-07-21xilinx: versal-net: Add mini eMMC 5.1 configurationAshok Reddy Soma
Add support for Versal NET mini eMMC 5.1 configuration. Add device tree and defconfig. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21xilinx: versal-net: Add mini ospi configurationAshok Reddy Soma
Add support for Versal NET mini Octal SPI flash configuration. This runs from onchip memory, so it has to be compact. Hence only Octal SPI related settings are enabled. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21xilinx: versal-net: Add mini qspi configurationAshok Reddy Soma
Add support for Versal NET mini Quad SPI flash configuration. This runs from onchip memory, so it has to be compact. Hence only Quad SPI related settings are enabled. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21cadence_qspi: Enable flash reset for Versal NET platformAshok Reddy Soma
Enable flash reset functionality for Versal NET platform. In cadence_qspi.c there is weak function defined for reset, hence remove the check for config, so that it will work for Versal and Versal NET platforms. Add register defines in Versal NET hardware.h for mini U-Boot flash reset. Add read_delay initialization for Versal NET also. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21arm64: zynqmp: Fix the memory node for k26/k24 kria som boardsSharath Kumar Dasari
PMUFW requires top 1MB of the lower DDR memory reserved for its operation, this is missing in k26/k24 sm static dts files because of which U-Boot throws warning messages "efi_free_pool: illegal free" as EFI puts some code to that space which shouldn't happen. Signed-off-by: Sharath Kumar Dasari <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/57452d16df2d48593de206bebf877d2c2cfe7bf1.1685966389.git.michal.simek@amd.com
2023-07-20Merge tag 'dm-pull-20jul23' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dm binman mkimage and template enhancements misc fixes
2023-07-21sunxi: H616: add LPDDR3 DRAM supportMikhail Kalashnikov
The H616 SoC has support for several types of DRAM: DDR3, LPDDR3, DDR4 and LPDDR4. At the moment, the driver only supports DDR3 memory. Let's extend the driver to support the LPDDR3 memory. All "magic" values obtained from the boot0. Signed-off-by: Mikhail Kalashnikov <[email protected]> Acked-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2023-07-21sunxi: H616: add DRAM type selectionMikhail Kalashnikov
Allwinner H616 SoC supports several types of DRAM memory. To further integrate other types of memory, we need to add this delimitation. Signed-off-by: Mikhail Kalashnikov <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2023-07-21sunxi: H616: dram: split struct dram_paraAndre Przywara
Currently there is one DRAM parameter struct for the Allwinner H616 DRAM "driver". It contains many fields that are compile time constants (set by Kconfig variables), though there are also some fields that are probed and changed over the runtime of the DRAM initialisation. Because of this mixture, the compiler cannot properly optimise the code for size, as it does not consider constant propagation in its full potential. Help the compiler out by splitting that structure into two: one that only contains values known at compile time, and another one where the values will actually change. The former can then be declared "const", which will let the compiler fold its values directly into the code using it. We also add "const" tags for some new "struct dram_config" pointers, to further increase code optimisation. To help the compiler optimise the code further, the definition of the now "const struct dram_para" has to happen at a file-global level, so move that part out of sunxi_dram_init(). That results in quite some code savings (almost 2KB), and helps to keep the code small with the LPDDR3 support added later. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21sunxi: H616: dram: const-ify DRAM function parametersAndre Przywara
There are quite some functions in the Allwinner H616 DRAM "driver", some of them actually change the parameters in the structure passed to them, but many are actually not. To increase the optimisation potential for the code, mark those functions that just read members of the passed dram_para struct as "const". This in itself does not decrease the code size, but lays the groundwork for future changes doing so. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21sunxi: dram: make MBUS configuration functions staticAndre Przywara
The usage of the C keyword "inline" seems to be a common misunderstanding: it's a *hint* only, and modern compilers will inline (or not) functions based on their own judgement and provided compiler options. So while marking functions as "inline" does not do much, missing the "static" keyword will force to compiler to spell out a version of the function for potential external callers, which actually increases the code size (though hopefully the linker will drop the function). Change the "inline" attribute for the mbus_configure_port() functions in some Allwinner DRAM drivers to "static", so that the explicit version can actually be dropped from the object file, reducing the code size. "static inline" has a use case in header files, where it avoids a warning if a .c file including this header does not use the particular function. In a .c file itself "static inline" is not useful otherwise, so just use static here as well. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21sunxi: Kconfig: rework PHY_USB_SUN4I selectionAndre Przywara
At the moment we use "select" in each Allwinner SoC's Kconfig section to include the USB PHY driver in the build. This means it cannot be disabled via Kconfig, although USB is not really a strictly required core functionality, and a particular board might not even include USB ports. Rework the Kconfig part by removing the "select" lines for each SoC's section, and instead letting it default to "y" in the PHY driver section itself. We use "depends on !" to exclude the few SoCs we don't support (yet). The Allwinner V3s does not enable USB (PHY) support at the moment, even though it should work: let the PHY default to "n" to keep the current behaviour. Also the MUSB USB driver directly calls some functions from the PHY driver, so let the former depend on the PHY driver. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Tested-by: Sam Edwards <[email protected]>
2023-07-20stm32mp15: Avoid writing symbols in SPLSimon Glass
These boards use SPL in a mkimage entry and apparently access the symbol containing the image position of U-Boot, but put U-Boot in another image. This means that binman is unable to fill in the symbol correctly in the SPL binary. This doesn't matter at present since mkimage doesn't support symbol writing. But with the upcoming conversion to a section, it will. So add a property to disable symbol writing. Signed-off-by: Simon Glass <[email protected]>
2023-07-20sandbox: fix a compilation errorSergei Antonov
With sandbox and sandbox64 configurations: In file included from .../u-boot/include/test/test.h:156, from .../u-boot/include/test/lib.h:9, from .../u-boot/test/lib/test_crc8.c:8: .../u-boot/arch/sandbox/include/asm/test.h: In function ‘sandbox_sdl_set_bpp’: .../u-boot/arch/sandbox/include/asm/test.h:323:17: error: ‘ENOSYS’ undeclared (first use in this function) 323 | return -ENOSYS; | ^~~~~~ Per Tom Rini's suggestion: move that function prototype over to arch/sandbox/include/asm/sdl.h and make test/dm/video.c include <asm/sdl.h> Cc: Simon Glass <[email protected]> Suggested-by: Tom Rini <[email protected]> Signed-off-by: Sergei Antonov <[email protected]> Reviewed-by: Simon Glass <[email protected]>
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