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This reverts commit b8ebf24e7f4afb5093a31bdf122e1ed0781e5c3c.
This patch seems to be fundamentally wrong and requires a different way
on how the background firewalls should be configured so revert the patch
Signed-off-by: Manorit Chawdhry <[email protected]>
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When build U-boot with clang with using commands:
$ make HOSTCC=clang xenguest_arm64_defconfig
$ make HOSTCC=clang CROSS_COMPILE=aarch64-linux-gnu- \
CC="clang -target aarch64-linux-gnueabi" -j8
The compiler reports error:
/tmp/start-acdf31.s:330:1: error: symbol '_start' is already defined
_start:
^
Because the symbol '_start' has been defined twice, one is defined in
arch/arm/cpu/armv8/start.S, another is defined in the header
boot0-linux-kernel-header.h.
To fix building failure, this patch removes the symbol '_start' from
boot0-linux-kernel-header.h.
Signed-off-by: Leo Yan <[email protected]>
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ARM requires a 4-byte alignment on all ARM code (though this
requirement is relaxed to 2-byte for some THUMB code) and we
should be explicit about that here.
GAS has its own fix for this[1] that forces proper alignment
on any section containing assembled instructions, but this is
not universal: Clang's and other gaslike assemblers lack this
implicit alignment. Whether or not this is considered a bug in
those assemblers, it is better to ask directly for what we want.
[1]: https://sourceware.org/bugzilla/show_bug.cgi?id=12931
Signed-off-by: Sam Edwards <[email protected]>
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Powerpc configurations are apparently able to do unaligned accesses. But
in an attempt to clean up and handle unaligned accesses in the same way
we ignore that and use the common asm-generic/unaligned.h directly
instead.
Signed-off-by: Jens Wiklander <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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M68k essentially duplicates the content of asm-generic/unaligned.h, with
an exception for non-Coldfire configurations. Coldfire configurations
are apparently able to do unaligned accesses. But in an attempt to clean
up and handle unaligned accesses in the same way we ignore that and use
the common asm-generic/unaligned.h directly instead.
Signed-off-by: Jens Wiklander <[email protected]>
Acked-by: Angelo Dureghello <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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Mips essentially duplicates the content of asm-generic/unaligned.h, so use
that file directly instead.
Signed-off-by: Jens Wiklander <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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Sh essentially duplicates the content of asm-generic/unaligned.h, so use
that file directly instead.
Signed-off-by: Jens Wiklander <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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Arm duplicates the content of asm-generic/unaligned.h, so use that file
directly instead.
Signed-off-by: Jens Wiklander <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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As part of various code clean-ups we have on occasion missed removing
unused header files. None of these files are referenced anywhere else
at this point.
Signed-off-by: Tom Rini <[email protected]>
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It seems like the header inclusion guard for some Uniphier DDR PHY
header was misspelled.
Make the preprocessor symbol for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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It seems like the header inclusion guards for some IMX related headers
were misspelled or got out of sync.
Make the preprocessor symbols for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This platform is currently unmaintained and untested, so remove it.
Further, as it is the only TI816X SoC example, remove related files as
well.
Signed-off-by: Tom Rini <[email protected]>
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Apple's M2 Pro/Max SoC are somewhat similar to the M1 Pro/Max but
need a tweaked memory map. USB, NVMe, UART and WDT are working
with the existing drivers.
Signed-off-by: Mark Kettenis <[email protected]>
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K3 GP devices allows booting the secure binaries on them by bypassing
the x509 header on them.
ATF and OPTEE firewalling required the rproc_load to be called before
authentication. This change caused the failure for GP devices that
strips off the headers. The boot vector had been set before the headers
were stripped off causing the runtime stripping to fail and stripping
becoming in-effective.
Separate out the secure binary check on GP/HS devices so that the
boot_vector could be stripped before calling rproc_load. This allows
keeping the authentication later when the cluster is on along with
allowing the stripping of the binaries in case of gp devices.
Fixes: 1e00e9be62e5 ("arm: mach-k3: common: re-locate authentication for atf/optee")
Signed-off-by: Manorit Chawdhry <[email protected]>
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When booting with HS silicon, the system firmware image is 278270, which
is slightly larger than currently allocated amount.
This can cause unexpected behavior if this overlap interferes with other
things in memory, so increase this with a slightly margin added as well
to avoid any boot issues that can appear after system firmware gets
loaded.
Signed-off-by: Dave Gerlach <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
Signed-off-by: Manorit Chawdhry <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
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In non-combined boot flow for K3, all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.
The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.
The commit changes R5 MCU scratchpad for j721e to an SRAM region.
Old Map:
┌─────────────────────────────────────┐ 0x41c00000
│ SPL │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│ STACK │
├─────────────────────────────────────┤ 0x41c85b20
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c85bfc
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41cf5bfc)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
New Map:
┌─────────────────────────────────────┐ 0x41c00000
│ SPL │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│ EMPTY │
├─────────────────────────────────────┤ 0x41c81920
│ STACK │
│ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │
├─────────────────────────────────────┤ 0x41c85920
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c859f0
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41cf59f0)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
├─────────────────────────────────────┤ 0x41cff9fc
│ NEW MCU SCRATCHPAD │
│ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
Fixes: ab977c8b91b4 ("configs: j721s2_evm_r5: Enable support for building multiple dtbs into FIT")
Signed-off-by: Manorit Chawdhry <[email protected]>
[[email protected]: SRAM allocation addressing diagram]
Signed-off-by: Neha Francis <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Kamlesh Gurudasani <[email protected]>
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When building for secure devices using non-buildman based image generation
the signed tispl.bin file is called tispl.bin_HS. Also build the unsigned
tispl.bin file as expected.
Signed-off-by: Andrew Davis <[email protected]>
Signed-off-by: Manorit Chawdhry <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20230525
-------------------
- i.MX93 series
- Fixes
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412
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To avoid using static setting for ECC enabled DDR size, switch
to calculate DDR size from DDRC setting
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Update the DDR init flow for multi-setpoint support on i.MX93. A new
fsp_cfg struct need to be added in the timing file to store the diff
part of the DDRC and DRAM MR register for each setpoint.
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add 625M bypass clock that may be used DRAM 625M
bypass mode support.
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap
specification does not include the Critical Delay Difference (CDD) to
properly define the required rank-to-rank read command spacing after
executing PHY training firmware.
Following the errata workaround, at the end of data training, we get
all CDD values through the MessageBlock, then re-configure the DDRC
timing of WWT/WRT/RRT/RWT with comparing MAX CDD values.
Signed-off-by: Ye Li <[email protected]>
Acked-by: Peng Fan <[email protected]>
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Add tmu nodes and thermal zone
Signed-off-by: Peng Fan <[email protected]>
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Sync device tree with next-20230426
Signed-off-by: Peng Fan <[email protected]>
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Currently bootaux only supports to boot M33 core from TCM. Since ATF
has changed to use x2 parameter for M33 image address, update the
bootaux command to use input address, so we can support boot from
any possilbe address like TCM, DDR, Flexspi NOR.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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There is no need to save gd with using the generic rom api function, so
simplify code.
Signed-off-by: Peng Fan <[email protected]>
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The end brace should be in a new line
Signed-off-by: Peng Fan <[email protected]>
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According to datasheet, iMX93 has fused parts with CORE1 or NPU or
both disabled. So update code to support it, the kernel device tree
runtime update will be added in future patches.
Signed-off-by: Peng Fan <[email protected]>
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Config the A55 alt root clock to 500MHz(LD mode frequency)
by default. Normally, this clock root is only used as an
intermediate clock soure for A55 core/dsu when change the
ARM PLL frequency.
Signed-off-by: Peng Fan <[email protected]>
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Add CONFIG_IMX9_LOW_DRIVE_MODE in imx9 clk, later we will
add board support
Signed-off-by: Peng Fan <[email protected]>
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The HW_CTRL_SEL should be cleared when configuring PLL to avoid
potential glitch
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Get the chip's market segment and speed grading from fuse and print
them in boot log as other i.MX series.
Signed-off-by: Peng Fan <[email protected]>
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Support print reset cause. Since SRSR is not accessible from non-secure
world, so first save it to grp0, then read it in non-secure world.
Signed-off-by: Peng Fan <[email protected]>
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The MAC addresses are hard coded for bring up. Change it to support
reading from fuse.
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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OPTEE memory region is set secure access only in ATF with configuration
to TRDC, and need to remove it from U-Boot, otherwise U-Boot and Kernel
may crash when accessing the memory
Signed-off-by: Peng Fan <[email protected]>
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Simplify the clk root settings with an array
Signed-off-by: Peng Fan <[email protected]>
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LPI2C_CLK_ROOT should be used instead of LPUART_CLK_ROOT for i2c
Signed-off-by: Peng Fan <[email protected]>
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The freq parameter was ignored, should use it when configuring ARM PLL
Signed-off-by: Peng Fan <[email protected]>
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Add more PLL settings for A55 and Display
Signed-off-by: Peng Fan <[email protected]>
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The M33 systick should be 24M per reference mannual, so correct it.
Signed-off-by: Peng Fan <[email protected]>
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Move imx8 sci header file to include/firmware/imx, then we could
use build macro to reuse some i.MX8 drivers for i.MX9, such as
drivers/cpu/imx8_cpu.c.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Stefano Babic <[email protected]>
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Unknow->Unknown
Signed-off-by: Peng Fan <[email protected]>
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The ahab was missed to be compiled, so add it back.
Signed-off-by: Peng Fan <[email protected]>
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Commit 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data
flags to set host caps") exposed the following SD card error:
U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300)
CPU: Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz)
CPU: Commercial temperature grade (0C to 95C) at 35C
Reset cause: POR
Model: Freescale i.MX7 SabreSD Board
Board: i.MX7D SABRESD in non-secure mode
DRAM: 1 GiB
Core: 100 devices, 19 uclasses, devicetree: separate
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... Card did not respond to voltage
select! : -110
*** Warning - No block device, using default environment
The reason of the problem, as explained by Ye Li:
"When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does
not configure pad for VSELECT, also the data pad should be set to
100Mhz/200Mhz pin states."
Apply these changes into u-boot.dtsi for now. When these changes
reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi.
This fixes UHS mode on the imx7d-sdb board.
Suggested-by: Ye Li <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Stop polluting the architecture directory with driver specific code,
move it into driver where it should be. Split the code slightly so
the MX8MM/MX8MN fuse readout and programming and MX8MP fuse readout
and programming are in their separate functions, and called in case
of matching SoC.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Andrejs Cainikovs <[email protected]>
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It seems like the ROM log events for the iMX8M are not fully covered by
AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event
ID 0x82 seems to use parameter0 which stops the parsing because the end
of list is detected too early.
This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is
parsed.
Fixes: a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM log")
Signed-off-by: Fedor Ross <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.
Similar to RK3568 the BootRom in RK3588 can read all data and look for
idbloader at 0x8000, same as on SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.
=> sf probe
SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1492992 bytes read in 129 ms (11 MiB/s)
=> sf update $fileaddr 0 $filesize
device 0 offset 0x0, size 0x16c800
1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s
The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does
not match the expected value of 3 (SPINOR) used by other SoCs. Instead a
value of 6 is read back, add a new enum value to handle this new
bootsource id.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Tested-by: Eugen Hristev <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
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Enable pinctrl for sdhci in SPL to support loading of FIT image from SD
and eMMC storage when booting from SPI NOR flash.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Like other Rockchip SoCs, DM_RESET and DM_REGULATOR_FIXED is useful
across RK3588 platform. Select them from arch Kconfig.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 3 Model A.
Unlike prior generation SoCs the BootRom in RK3568 can read all data and
look for idbloader at 0x8000, same as on SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.
=> sf probe
SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1384448 bytes read in 119 ms (11.1 MiB/s)
=> sf update $fileaddr 0 $filesize
device 0 offset 0x0, size 0x152000
1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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