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Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add
missing supported mmc modes to sdhci node.
Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config option to include useful gpio cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.
Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add bootph-all prop to xin24m clock node, it is referenced by cru node.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable the PCIe 2x1l 2 device and associated combphy.
On this bus, the Rock5B has an Ethernet transceiver connected.
Signed-off-by: Christopher Obbard <[email protected]>
[[email protected]: minor tweaks]
Signed-off-by: Eugen Hristev <[email protected]>
[[email protected]: add PCIe pins]
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add the node for PCIe 2x1l 2 device together with the corresponding
combphy.
Signed-off-by: Joseph Chen <[email protected]>
[[email protected]: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev <[email protected]>
[[email protected]: adapt to kernel node]
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable the use of SDMA mode to boost eMMC performance on ROCK Pi 4.
Also add missing flags to indicate the supported MMC modes.
Using mmc read command to read 32 MiB data shows following improvement:
=> time mmc read 10000000 2000 10000
Before: time: 3.178 seconds
After: time: 0.402 seconds
This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable the use of SDMA mode to boost eMMC performance on RockPro64.
Also add missing flags to indicate the supported MMC modes.
Using mmc read command to read 32 MiB data shows following improvement:
=> time mmc read 10000000 2000 10000
Before: time: 3.178 seconds
After: time: 0.402 seconds
This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399
similar to other Rockchip SoCs. Checksum validation fails with:
## Checking hash(es) for Image atf-2 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-2' image node
spl_load_simple_fit: can't load image loadables index 1 (ret = -1)
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Add a device tree property, u-boot,spl-fifo-mode, to control when the
rockchip_sdhci driver should disable the use of DMA and fallback on PIO
mode. Same device tree property is used by the rockchip_dw_mmc driver.
In commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") the DMA mode was disabled using a CONFIG
option on RK3588. Revert that and instead disable DMA using the device
tree property for all RK3588 boards, also apply similar workaround for
all RK3399 boards.
Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Tested-by: Quentin Schulz <[email protected]> # RK3399 Puma, RK3588 Tiger
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The current DT bindings for the rk3588 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.
This approach has been implemented already in Linux, by commit :
f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")
Hence, implement a similar approach using the lookup table, and adapt
the existing reset driver to work with SoCs using lookup table.
The file rst-rk3588.c has been copied as much as possible from Linux.
Adapt the clk rk3588 driver as well to bind the reset driver with the
lookup table.
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Eugen Hristev <[email protected]>
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To be able to initialize the pinctrl correctly at SPL level and read
u-boot proper from SD-Card, the pinctrl must be initialized.
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add USB 2.0 host nodes and PHYs.
Reviewed-by: Kever Yang <[email protected]>
Co-developed-by: William Wu <[email protected]>
Signed-off-by: William Wu <[email protected]>
Signed-off-by: Eugen Hristev <[email protected]>
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- Merge in a long-standing fix for some exynos platforms, correct a
Kconfig description, fix some env issues, fix an issue in
devfdt_get_addr_size_index_ptr and look for "panel-timings" not
"panel-timing" per upstream binding.
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.07-rc3
.mailmap
- Fix Xilinx IDs
ZynqMP:
- Fix R5 split boot mode
- DT fixes - sync with Linux
Xilinx:
- Enable virtio and RNG support
- Enable ADI ethernet phy
SPI/Zynq:
- Fix dummy byte calculation
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In case where a single timing resolution is implemented in the
device-tree, the property is named "panel-timing", as specify
in Linux kernel binding file:
Documentation/devicetree/bindings/display/panel/panel-common.yaml
# Display Timings
panel-timing:
description:
Most display panels are restricted to a single resolution and
require specific display timings. The panel-timing subnode expresses those
timings.
$ref: panel-timing.yaml#
display-timings:
description:
Some display panels support several resolutions with different timings.
The display-timings bindings supports specifying several timings and
optionally specifying which is the native mode.
$ref: display-timings.yaml#
Fixes: 0347cc773270 ("drivers: core: ofnode: Add panel timing decode.")
Signed-off-by: Raphael Gallais-Pou <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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The commit c8630167e0dc ("arm64: zynqmp: Add mtd partition for secure OS
storage area") didn't update User partition size that's why size was beyond
actual device size.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/0a56405553b87a75e066cd71697cafe7c1c97eef.1681309812.git.michal.simek@amd.com
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In current implementation, applications can execute only on R5 core 0.
The boot address for R5 core 1 is not supplied. Pass TCM address for
R5 core 1 based on the argument to fix the issue.
Remove incomplete comment.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/da865717d26648ab7a84345ca8749712efdddee5.1680699999.git.michal.simek@amd.com
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Fix model name, node locations and also add pinctrl description for usb.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/3295fde73db13a712b65f4967eb5f39ced895ad4.1679988091.git.michal.simek@amd.com
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Switch to earlycon which is preffered over earlyprintk.
It is also sync with Linux kernel (zynq-microzed).
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/d280fa18068f80412cf12c235c5245651e7062e2.1679987839.git.michal.simek@amd.com
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The "zynqmp tcminit split" command should halt both cores and not just RPU1
when configuring the TCM memory for split mode.
Signed-off-by: Neal Frager <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-sh
- R-Car RZN1 support
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We use the terms 'distro' to mean extlinux but they are not really the
same. 'Distro' could refer to any method of booting a distribution,
whereas extlinux is a particular method.
Also we sometimes use syslinux, but it is better to use the same term in
all cases.
Rename distro to syslinux and also update bootstd uses of syslinux to use
extlinux instead.
Signed-off-by: Simon Glass <[email protected]>
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Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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These are not used in TPL so disable the drivers to save space.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This copies the cpu_call64() function to memory address and then jumps to
it. This seems to work correctly even when called from SPL, which is
running from SPI flash.
Drop the copy as it is not needed.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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We don't need to commit the SPI-flash MTRR change immediately, since it is
now done in the board_init_f_r(). Also this causes chromebook_link64 to
hang, presumably since we are still running from CAR (Cache-as-RAM) in
SPL. Coral handles this OK, perhaps since it is running from a different
memory area, but it has no effect on Coral anyway.
Drop the extra mtrr_commit() in the SPL implementation.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This function is used by U-Boot proper. It does not set up MTRRs when SPL
is enabled, but we do want this done when it is called from SPL. In fact
it is confusing to use the same function from SPL, since there are quite
a few conditions there.
All init_cache_f_r() really does is commit the MTRRs and set up the cache.
Do this in the SPL's version of this function instead.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Use the binman symbols for this, to avoid hard-coding the value. We could
use CONFIG_X86_OFFSET_U_BOOT for the address, but it seems better to
obtain the offset and size through the same mechanism.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Show the area of memory cleared for BSS, when debugging is enabled.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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SPL printf() does not normally support %#x so just use %x instead. Hex is
expected in U-Boot anyway.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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For now, just enable the fast-but-large string functions in 32-boot
U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit
builds since we only have 32-bit assembly.
Reviewed-by: Bin Meng <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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The debug UART is already set up in SPL, so there is no need to do
anything here. We must provide the (empty) function though.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The bd82x6x_get_gpio_base() does not work if the LPC is not set up.
Probe it early to avoid this problem.
In chromebook_link64 this problem shows up as an inability to read
the GPIO straps for the memory type.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intent of the
original call. Fix this by renaming and updating the calling logic.
With this, chromebook_link64 makes it through SPL.
Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Sometimes coreboot adds new tags that U-Boot does not know about. These
are silently ignored, but it is useful to at least know what we are
missing.
Add a way to collect this information. For Brya it shows:
Unimpl. 38 41 37 34 42 40
These are:
LB_TAG_PLATFORM_BLOB_VERSION
LB_TAG_ACPI_CNVS
LB_TAG_FMAP
LB_TAG_VBOOT_WORKBUF
LB_TAG_TYPE_C_INFO
LB_TAG_BOARD_CONFIG
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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At present any ACPI tables created by prior-stage firmware are ignored.
It is useful to be able to view these in U-Boot.
Pick this up from the sysinfo tables and display it with the cbsysinfo
command. This allows the 'acpi list' command to work when booting from
coreboot.
Adjust the global_data condition so that acpi_start is available even if
table-generation is disabled.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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We have several Kconfig options for ACPI, but all relate to specific
functions, such as generating tables and AML code.
Add a new option which controls including basic ACPI library code,
including the lib/acpi directory. This will allow us to add functions
which are available even if table generation is not supported.
Adjust the command to avoid a build error when ACPIGEN is not enabled.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Avoid searching starting at 0 since this memory may not be available,
e.g. if protection against NULL-pointer access is enabled. The table
cannot be there anyway, since the first 1KB of memory was originally
used for the interrupt table and coreboot avoids it.
Start at 0x400 instead.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This avoid an error with enable_sata_clock when
defined(CONFIG_SATA) is changed to CONFIG_IS_ENABLED(SATA).
Signed-off-by: Troy Kisky <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
would check for CONFIG_SPL_SPL_X86_32BIT_INIT for SPL builds
Signed-off-by: Troy Kisky <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Rockchip NFC driver update and dev addr pointer api update;
- use standard dr_mode for usb driver;
- rock pi boards dts update;
- Add rk3566 Anbernic boards;
- Misc fixes for drivers;
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The OTG port is identified by inspecting the "dr_mode" property which is
expected to be "otg" for this port. But it will work just as well as a
device controller when dr_mode is set to "peripheral", which may be
required if the mode detection pin is not set up correctly and the
device controller needs to be programmed to override this.
Signed-off-by: John Keeping <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Instead of duplicating the string values here, use usb_get_dr_mode() to
handle the property lookup and converting the values to an enum.
This is implemented with a switch in preparation for the next patch
which adds extra handling for peripheral mode.
Signed-off-by: John Keeping <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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use common one defined in rk356x-u-boot.dtsi.
Signed-off-by: FUKAUMI Naoki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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sort alphanumerically.
Signed-off-by: FUKAUMI Naoki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Linux commit 246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+
Add support for Radxa ROCK 4C+ SBC.
Key differences of 4C+ compared to previous ROCK Pi 4.
- Rockchip RK3399-T SoC
- DP from 4C replaced with micro HDMI 2K@60fps
- 4-lane MIPI DSI with 1920*1080
- RK817 Audio codec
Also, an official naming convention from Radxa mention to remove
Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not
Radxa ROCK Pi 4C+.
Signed-off-by: Stephen Chen <[email protected]>
Signed-off-by: Manoj Sai <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Signed-off-by: FUKAUMI Naoki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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sync dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3.
because rk3399-rock-pi-4a.dts is enough for ROCK Pi 4A/B/A+/B+ and ROCK
4SE, delete dts{,i} for ROCK Pi 4B.
Signed-off-by: FUKAUMI Naoki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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