| Age | Commit message (Collapse) | Author |
|---|
|
The FSPI header is now generated purely using binman, drop no longer
supported nxp,fspi-header-filename property.
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
|
|
Select TQ_COMMON_SYSINFO to use the tq_eeprom sysinfo driver
to read and print module EEPROM data.
Signed-off-by: Max Merchel <[email protected]>
|
|
Add sysinfo node for tq,eeprom sysinfo driver.
Signed-off-by: Max Merchel <[email protected]>
|
|
TQMa6UL has board-information located in EEPROM at offset 0x20.
Add necessary nodes and properties for nvmem-cells.
Revert this commit once the upstream linux device trees are
accepted and synchronized.
Signed-off-by: Max Merchel <[email protected]>
|
|
Since b57ed147939c ("dts: imx8m{m,n,p,q}: Make optee packaging optional")
the TEE node is always present in U-Boot proper fitImage, even if the
CONFIG_OPTEE is disabled because the u-boot.itb should not contain any
tee.bin. This is wasteful, and produces the following warning which is
also confusing to users:
"
Image 'image' is missing optional external blobs but is still functional: tee-os
/binman/section/fit/images/tee/tee-os (tee.bin):
See the documentation for your board. You may need to build Open Portable
Trusted Execution Environment (OP-TEE) and build with TEE=/path/to/tee.bin
"
Reinstate the CONFIG_OPTEE ifdeffery to mitigate the problem, but retain the
binman "optional" keyword at tee.bin .
Before:
"
$ mkimage -l u-boot.itb
FIT description: Configuration to load ATF before U-Boot
Created: Tue Jun 30 17:23:54 2026
Image 0 (uboot)
...
Image 2 (tee) <------------------------------ bogus empty image entry
Description: OP-TEE |
Created: Tue Jun 30 17:23:54 2026 |
Type: Trusted Execution Environment Image |
Compression: uncompressed |
Data Size: 0 Bytes = 0.00 KiB = 0.00 MiB <--------'
Image 3 (fdt-1)
...
"
After:
"
$ mkimage -l u-boot.itb
FIT description: Configuration to load ATF before U-Boot
Created: Tue Jun 30 17:58:15 2026
Image 0 (uboot)
...
Image 1 (atf)
...
Image 2 (fdt-1)
...
"
Fixes: b57ed147939c ("dts: imx8m{m,n,p,q}: Make optee packaging optional")
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
|
|
DQS gating calibration
The current DRAM calibration sequence is implemented based on NXP
AN4467 Rev.2 03/2015, which in chapter "12.3.2 Calibration Sequence
Setup with Predefined Data Content" states:
"
9. For each of the DQSx:
- Read the HW_DG_UPx value from the MMDC0/1_MPDGHWSTx, subtract the
value of 0xc0 (3/4 cycle).
"
However, the i.MX 6Solo/6DualLite Applications Processor Reference
Manual, Rev. 5, 05/2020, chapter "45.11.3.1.2 Hardware DQS Calibration
with pre-defined value" states:
"
35. Set (MPDGHWSTn[HW_DG_UPn][10:7] - 1) to MPDGCTRLn[DG_HC_DELn].
(We set the DQS gating value to be the upper limit value minus
1 half cycle)
"
The i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 6,
05/2020, chapter 44.11.3.1.2 Hardware DQS Calibration with pre-defined
value lists the same information. So do the following manuals:
- i.MX 6DualPlus/6QuadPlus Applications Processor Reference Manual, Rev. 3, 05/2020
chapter 46.11.3.1.2 Hardware DQS Calibration with pre-defined value
- i.MX 6SoloX Applications Processor Reference Manual, Rev. 4, 05/2020
chapter 40.11.3.1.2 Hardware DQS Calibration with pre-defined value
- i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017
chapter 33.11.3.1.2 Hardware DQS Calibration with pre-defined value
- i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017
chapter 35.11.3.1.2 Hardware DQS Calibration with pre-defined value
- i.MX 6ULZ Applications Processor Reference Manual, Rev. 0, 10/2018
chapter 29.11.3.1.2 Hardware DQS Calibration with pre-defined value
The NXP MMDC DDR Stress Test (3.0.0) tool seems to be have the same
way as the later document rather than the AN4467 application note,
and produces values similar to the values with subtracted 1/2 cycle.
Adjust the behavior to match the more recent Reference Manual and
the MMDC calibration tool.
Winbond W634GU6RB does show sporadic signs of instability without
this correction.
Signed-off-by: Marek Vasut <[email protected]>
Tested-by: Christoph Niedermaier <[email protected]>
|
|
Because the i2c address of some gpio expander devices are same, so
in dts they have same node name which lead to same gpio device name.
Users can't get the GPIO through GPIO API or GPIO command.
Add the label to each gpio expander node, hence give unique name.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
|
|
Check the GPIO2 dts node status to determine reset it or not.
On iMX952 single SPL/U-Boot image is shared for both mx952evk
and mx952evkrpmsg SM configs. GPIO2 is assigned to M7 domain
in mx952evkrpmsg, and there is no active user of GPIO2 for
mx952evk and mx952evkrpmsg in SPL/U-Boot, so it is disabled in
DTS. Otherwise, reset GPIO2 will meet hang when working with
mx952evkrpmsg SM.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
When working with SM config mx9{4,5,52}evkrpmsg, mcores are not booted
by ROM. Hence, power on the mcore and initialize TCM ECC in u-boot for
subsequent mcore booting.
Signed-off-by: Ye Li <[email protected]>
[fabio: Adapted to mainline context]
Signed-off-by: Fabio Estevam <[email protected]>
|
|
Support booting CM70, CM71 and CM33 sync core image by bootaux command
on iMX95, iMX94 and iMX952. (iMX95 and iMX952 only supports CM70).
Each core uses different core id which is defined by SM and passed in
SIP call.
- CM33: 0
- CM70: 1
- CM71: 7
- CM33S: 8
Prior to run bootaux to start core, prepaux is needed before loading
image. Below is example for booting CM70 TCM image on iMX95.
=>fatload mmc 1:1 0x90000000 rpmsg.bin
=>prepaux 1
=>cp.b 0x90000000 0x203c0000 ${filesize}
=>bootaux 0 1
Signed-off-by: Alice Guo <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Jacky Bai <[email protected]>
|
|
Add new command bootaux_cntr to replace bootaux in secure boot
(CONFIG_AHAB_BOOT=y) to authenticate signed M33 core image.
The M33 image must be packed in container format and signed.
bootaux_cntr supports Mcore image loaded to TCM or run as
FlexSPI NOR XIP.
Signed-off-by: Ye Li <[email protected]>
[fabio: Adapted to use gd->dram[i]]
Signed-off-by: Fabio Estevam <[email protected]>
|
|
Although it has similar naming the Librem 5 Devkit is a completely
different design from the Librem 5 phone. It uses an imx8mq SOM from
Emcraft, a separate HDMI port instead of DisplayPort, different USB-C
chip, panel, etc.
This is based on a Emcraft's SOM documentation, Purism's downstream fork
and the available schematics of the devkit.
Link: https://developer.puri.sm/Librem5/Development_Environment/Boards/imx8.html
Link: https://source.puri.sm/Librem5/dvk-mx8m-bsb
Co-authored-by: Angus Ainslie <[email protected]>
Co-authored-by: Manuel Traut <[email protected]>
Signed-off-by: Manuel Traut <[email protected]>
Tested-by: Manuel Traut <[email protected]>
Signed-off-by: Guido Günther <[email protected]>
[fabio: Removed the arch/arm/dts/Makefile entry that does not apply and
it is not needed as the board uses OF_UPSTREAM]
Signed-off-by: Fabio Estevam <[email protected]>
|
|
log_debug() cannot be used before log_init() has been called. Remove the
log_debug() statement in enable_caches() since it is called before
log_init() in initcall_run_r().
This fixes a bug where a RISC-V system which does not have the "zicbom"
extension (such as PIC64-HPSC/HX) would get lost in an infinite loop in
log_dispatch().
Fixes: 9e859849e2ca ("riscv: cache: Add CBO instructions")
Signed-off-by: Charles Perry <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
A platform (like Xilinx Microblaze V) does not have an ACLINT (Advanced
Core Local Interruptor) hardware block.
Make RISCV_ACLINT and SPL_RISCV_ACLINT Kconfig symbols visible with
prompts.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Yao Zi <[email protected]>
|
|
Building on commit c64fc632a86a ("riscv: cpu: Use CONFIG_IS_ENABLED(CPU)
instead of plain ifdef"), add an early return in riscv_cpu_setup() when
CONFIG_CPU is not enabled. This allows platforms to save code space in
SPL by disabling CONFIG_SPL_CPU.
Without this patch, building U-Boot with CONFIG_CPU=n and CONFIG_EVENT=y
is broken: riscv_cpu_setup() is registered as an EVT_DM_POST_INIT_F event
spy, and when the CPU uclass is unavailable uclass_find_first_device()
returns no device, so the function returns -ENODEV. That in turn makes
event_notify_null() in dm_init_and_scan() fail and triggers a boot hang
("initcall initf_dm() failed"). Returning 0 early avoids that failure.
The compiler's dead-code elimination combined with --gc-sections
removes the unreachable code and all associated static data,
achieving significant size reduction without preprocessor guards:
spl/u-boot-spl:all -4332 spl/u-boot-spl:rodata -2872
spl/u-boot-spl:text -1460
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Yao Zi <[email protected]>
|
|
Fix warning:
arch/riscv/dts/cv18xx.dtsi:208.26-216.5: Warning (spi_bus_bridge):
/soc/spi-nor@10000000: node name for SPI buses should be 'spi'
Signed-off-by: Hiago De Franco <[email protected]>
|
|
The upstream Linux kernel relies on the sunxi_sram driver to bind the
system-control nodes as syscon devices. Since U-Boot lacks this SRAM
driver, peripheral drivers may fail to resolve the syscon node unless an
explicit "syscon" compatible is added into the device tree.
To address this, add a bare UCLASS_SYSCON driver that matches all
Allwinner system-control and SRAM controller compatibles listed in the
Linux kernel to provide the necessary regmap access to the system
controller.
Signed-off-by: Junhui Liu <[email protected]>
|
|
The SPI IP in the Allwinner A523 is mostly compatible to the later
generation used in other Allwinner SoCs, at least as far as the SPL
driver is concerned.
Just add the pinmux configuration for SPI0 on PortC, as used by the
BROM. This enables SPI (NOR) boot on A523/A527/T527 boards.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
|
|
The function to set the pinmux for the Port C SPI0 pins was looking more
like a logic puzzle from a magazine than something that readers could
understand and extend.
Replace the convoluted pinmux setup, grouped by pin, with a simple array
of the four pins involved, and just initialise this array at build time,
based on the selected SoC.
This makes it easy to see which pins are needed, and even easier to extend.
Signed-off-by: Andre Przywara <[email protected]>
|
|
DCACHE_OFF is defined as (0 << 2) = 0, and PTE_TYPE_FAULT is defined
as (0 << 0) = 0. In mmu_set_region_dcache_behaviour(), the cache
attribute passed to set_regions() is computed as:
attrs = PMD_ATTRINDX(option >> 2)
For DCACHE_OFF=0 this evaluates to PMD_ATTRINDX(0) = 0, which equals
PTE_TYPE_FAULT.
Commit 6468ca13ffd6f ("armv8: mmu: fix and optimise explicitly unmapping
regions") added an unmap path to set_one_region() that
triggers when attrs == PTE_TYPE_FAULT. Because DCACHE_OFF and
PTE_TYPE_FAULT share the same numerical value (0), any call to
mmu_set_region_dcache_behaviour() with DCACHE_OFF silently unmaps the
target region instead of changing its cache attributes to non-cached.
The subsequent flush_dcache_range() call at the end of
mmu_set_region_dcache_behaviour() then crashes with a Level 3
translation fault because the region it tries to flush has just been
unmapped.
The existing flag parameter already distinguishes the two callers:
- mmu_set_region_dcache_behaviour() always passes flag=false
- mmu_change_region_attr_nobreak() always passes flag=true, and is the
only legitimate caller that passes PTE_TYPE_FAULT to unmap a region
Guard the unmap path with flag so that DCACHE_OFF attribute changes
take the correct else branch, which ORs in the ATTRINDX bits only,
leaving the PTE valid.
This was observed as a boot crash on Versal, Versal Net, and ZynqMP
platforms during network initialisation. The zynq_gem driver calls
mmu_set_region_dcache_behaviour() with DCACHE_OFF to make its BD
descriptor ring non-cached. With the bug the BD memory is unmapped,
and the subsequent dcache flush inside
mmu_set_region_dcache_behaviour() faults.
Fixes: 6468ca13ffd6f ("armv8: mmu: fix and optimise explicitly unmapping regions")
Signed-off-by: Akshay Belsare <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
|
|
The ROC-RK3588S-PC board is an SBC made by Firefly, based on the RK3588S
SoC.
Add support for it.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/[email protected]
[s/ROC-PC-RK3588S/ROC-RK3588S-PC/ in commit log and diff]
Signed-off-by: Quentin Schulz <[email protected]>
|
|
The use of RK_FUNC_n defines is deprecated in the upstream
rockchip.h file. Replace all them by the function number.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Quentin Schulz <[email protected]>
|
|
The GPT-based capsule update helpers match updatable images by
partition type GUID and fail to build if PARTITION_TYPE_GUID is not
enabled:
arch/arm/mach-rockchip/board.c:50:29: error: 'struct disk_partition'
has no member named 'type_guid'
Boards which keep their firmware on SPI-NOR use a static dfu_string
instead of scanning GPT partitions and have no use for this code, so
guard it accordingly.
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Fixes: bea9267d7e6d ("rockchip: capsule: Add functions for supporting capsule updates")
Link: https://patch.msgid.link/af0ac32e2bf603c39f490f15fe62319fd73c5282.1784423864.git.daniel@makrotopia.org
Signed-off-by: Quentin Schulz <[email protected]>
|
|
Change driver names for MediaTek mt8516 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-14-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
|
|
Change driver names for MediaTek mt7629 clocks to be globally unique.
This will allow better build bot testing by allowing all clocks to be
compiled at the same time.
Link: https://patch.msgid.link/20260707-mtk-clk-unique-driver-names-v1-3-283d9a55361e@baylibre.com
Signed-off-by: David Lechner <[email protected]>
|
|
Remove all clock-parent properties from mt7988.dtsi. The clock driver
for this no longer uses this property. And this property would not be
acceptable upstream anyway.
Link: https://patch.msgid.link/20260710-mtk-clk-parent-lookup-improvements-v2-23-f3f3a4a28dca@baylibre.com
Signed-off-by: David Lechner <[email protected]>
|
|
Remove all clock-parent properties from mt7986.dtsi. The clock driver
for this no longer uses this property. And this property would not be
acceptable upstream anyway.
Link: https://patch.msgid.link/20260710-mtk-clk-parent-lookup-improvements-v2-22-f3f3a4a28dca@baylibre.com
Signed-off-by: David Lechner <[email protected]>
|
|
Remove all clock-parent properties from mt7981.dtsi. The clock driver
for this no longer uses this property. And this property would not be
acceptable upstream anyway.
Link: https://patch.msgid.link/20260710-mtk-clk-parent-lookup-improvements-v2-21-f3f3a4a28dca@baylibre.com
Signed-off-by: David Lechner <[email protected]>
|
|
Remove a duplicate topckgen override setting `bootph-all;`. The same
code was written twice in a row (probably copy/paste leftover).
Link: https://patch.msgid.link/20260708-mtk-mt7623-remove-dup-dt-override-v1-1-efffd4b6c12a@baylibre.com
Signed-off-by: David Lechner <[email protected]>
|
|
U-Boot applies DTS overrides by searching for files in the following
priority order [1]:
<orig_filename>-u-boot.dtsi
<CONFIG_SYS_SOC>-u-boot.dtsi
<CONFIG_SYS_CPU>-u-boot.dtsi
<CONFIG_SYS_VENDOR>-u-boot.dtsi
u-boot.dtsi
For Genio 510 and Genio 700, the common mt8188-u-boot.dtsi override is
never applied because none of the lookup paths resolve to it
(CONFIG_SYS_SOC="mediatek", CONFIG_SYS_CPU="armv8",
CONFIG_SYS_VENDOR="mediatek").
Add board-specific overrides for mt8370-genio-510-evk and
mt8390-genio-700-evk that include mt8188-u-boot.dtsi.
While at it, also add mt8188-u-boot.dtsi into
board/mediatek/MAINTAINERS.
[1]: https://docs.u-boot.org/en/stable/develop/devicetree/control.html#adding-tweaks-for-u-boot
Signed-off-by: Julien Stephan <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://patch.msgid.link/20260701-fix-genio-510-genio-700-dts-override-v1-1-cb571f8c9296@baylibre.com
Signed-off-by: David Lechner <[email protected]>
|
|
Rasmus Villemoes <[email protected]> says:
This started by me wanting something like what patch 8 does. That
wasn't too hard, except we had no strcasestr(), and also our regex
engine (which I didn't really want to pull into the mix anyway)
doesn't have a flag that requests case-insensitive matching. So I
wanted to add strcasestr(), but then I stumbled on a bunch of stuff
that should be cleaned up in str-land.
Link: https://lore.kernel.org/r/[email protected]
|
|
First, remove the !__KERNEL__ block, since U-Boot is always compiled
with -D__KERNEL__.
Second, remove the mention of the non-existing file
arch/sh/lib/strcasecmp.c and the redundant declaration of strcasecmp()
If sh did have a strcasecmp.c file, presumably the header would have
had to #define __HAVE_ARCH_STRCASECMP.
Third, remove the explicit #undefs of various __HAVE_ARCH_* and
redundant declarations of standard functions, which are anyway
declared in linux/string.h. In the linux source tree, those are all
#defines, and indeed linux does have asm implementations of those functions.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Rasmus Villemoes <[email protected]>
|
|
When CONFIG_MULTI_DTB_FIT is enabled, the FIT image contains multiple
device tree configurations for different boards. The default
configuration must be explicitly set to ensure the FIT framework
traverses all available configurations instead of falling back to
CONFIG_DEFAULT_DEVICE_TREE.
Without this default property, fit_find_config_node() will use
CONFIG_DEFAULT_DEVICE_TREE as the configuration name to match.
This prevents the SPL from correctly selecting the appropriate
DTB based on runtime board detection (e.g., from EEPROM).
Remove the conditional guard so that "default = conf-1" is always
present in the FIT image, regardless of CONFIG_MULTI_DTB_FIT.
Signed-off-by: Raymond Mao <[email protected]>
Signed-off-by: Guodong Xu <[email protected]>
|
|
Add nor_early_init() to probe the QSPI controller and SPI NOR flash
in SPL. Switch spl_boot_device() to BOOT_DEVICE_SPI so the board
boots from SPI flash.
Change the default device tree to k1-musepi-pro, whose u-boot
overlay already defines the QSPI controller and flash node with
bootph-pre-ram markers. Enable the required SPI driver model and
flash config options.
Signed-off-by: Guodong Xu <[email protected]>
|
|
Add Spacemit P1 SoC support in SPL. And set the default voltage
for BUCKs and LDOs.
Also update MAINTAINERS: add Guodong Xu as co-maintainer, list the
u-boot-spacemit mailing list, register the new K1 driver files (i2c,
PMIC, regulator), and fix a pre-existing '@@' typo in Huan Zhou's
email.
Fixes: 1cd239f44438 ("riscv: spacemit: bananapi_f3: initial support added")
Signed-off-by: Raymond Mao <[email protected]>
Signed-off-by: Guodong Xu <[email protected]>
Tested-by: Songsong Zhang <[email protected]>
|
|
Include DDR initialization firmware in the SPL image. The firmware
path can be specified via the DDR_FW_FILE environment variable. If
the firmware is not found, an empty placeholder file is created to
allow the build to proceed without DDR initialization support.
Signed-off-by: Raymond Mao <[email protected]>
Signed-off-by: Guodong Xu <[email protected]>
Tested-by: Songsong Zhang <[email protected]>
|
|
And support for required components including clock, I2C controller,
and I2C EEPROM.
Signed-off-by: Raymond Mao <[email protected]>
Signed-off-by: Guodong Xu <[email protected]>
Tested-by: Songsong Zhang <[email protected]>
|
|
Make the K1 clock controllers visible to SPL by tagging the four root
fixed clocks (osc_32k, vctcxo_{1,3,24}m) and the four syscon nodes
(mpmu, pll, apmu, apbc) with bootph-pre-ram in the BPI-F3 U-Boot
overlay.
Signed-off-by: Raymond Mao <[email protected]>
Signed-off-by: Guodong Xu <[email protected]>
Tested-by: Songsong Zhang <[email protected]>
|
|
Add SPL support featuring debug UART output for early boot
diagnostics on K1 SoC.
Signed-off-by: Raymond Mao <[email protected]>
Signed-off-by: Guodong Xu <[email protected]>
Tested-by: Songsong Zhang <[email protected]>
|
|
Restructure K1 SoC support to handle multiple boards through a single
configuration:
1. Rename bananapi-f3_defconfig to spacemit_k1_defconfig.
2. Move all K1 board files to board/spacemit/k1/.
3. Replace TARGET_BANANAPI_F3 with TARGET_SPACEMIT_K1 and rename the
board's <board>.h header to k1.h.
Eliminates the need for board-specific defconfigs while maintaining
hardware compatibility.
Signed-off-by: Raymond Mao <[email protected]>
Signed-off-by: Guodong Xu <[email protected]>
Link: https://patch.msgid.link/[email protected]
Tested-by: Songsong Zhang <[email protected]>
|
|
The K1 build now consumes the kernel device tree via OF_UPSTREAM. The
local copies under arch/riscv/dts/ (k1.dtsi, k1-pinctrl.dtsi,
k1-bananapi-f3.dts) are unreachable; remove them.
Signed-off-by: Guodong Xu <[email protected]>
|
|
Adopt the kernel device tree directly from
dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts instead of carrying
a forked copy under arch/riscv/dts/.
The U-Boot-only overlay k1-bananapi-f3-u-boot.dtsi carries the binman
description and a memory@0 node, since the upstream kernel DT has no
memory node (RAM is filled in by the bootloader).
Signed-off-by: Guodong Xu <[email protected]>
|
|
As part of moving our git forge to a new location, update all references
in tree to point to git.u-boot-project.org now.
Signed-off-by: Tom Rini <[email protected]>
|
|
Add support for the Anbernic RG-DS dual-screen handheld gaming device.
Link: https://anbernic.com/products/rgds
Signed-off-by: Chris Morgan <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Link: https://patch.msgid.link/[email protected]
[conflict resolution in doc/board/rockchip/rockchip.rst due to commit
b5deaa71fbe5 ("board: rockchip: Add support for 9Tripod X3568 v4")]
Signed-off-by: Quentin Schulz <[email protected]>
|
|
The pinctrl settings are now upstream, with the upstream
voltage supplies, and the HS200 mode is confirmed to work
fine but the HS400 mode had reported issues so let's just
consume what the upstream DT has now as it's all known good.
Reported-by: Dusty Mabe <[email protected]>
Tested-by: Dusty Mabe <[email protected]>
Signed-off-by: Peter Robinson <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Quentin Schulz <[email protected]>
|
|
I had missed that this series was no longer ready to merge as there are
other issues to resolve.
This reverts commit a5ef1849394de475ee3bb9ebfc7629b4dd3b746a, reversing
changes made to 4e7a9bb0885e75853687956002e69875e0ef64e6.
Signed-off-by: Tom Rini <[email protected]>
|
|
area"
Aristo Chen <[email protected]> says:
vbe_read_fit() loads a firmware-phase FIT from a fixed firmware area on
a block device and then issues a follow-up blk_read() to pull in the
image, and optionally an FDT, referenced by the FIT's image node. The
source offset on the device and the read length both come from the FIT
itself, via data-position or data-offset and data-size. Those properties
live on mutable boot media and can be controlled by an attacker with
write access to the firmware area. On the TPL or VPL path, and on the
bootmeth bootflow path reached via abrec_read_bootflow_fw() and
vbe_simple_read_bootflow_fw(), the follow-up blk_read() runs before any
signature or hash check on the loaded phase.
Patch 1 is a sandbox test-tree preparation. The firmware1 node in
arch/sandbox/dts/test.dts declared area-size = 0xe00000 (14 MiB), but
the binman fw-update section in sandbox_vpl.dtsi is 32 MiB and the FIT
inside it carries ~16 MiB of external data, so the FIT already extended
past the declared area. The mismatch was tolerated because no caller
bounded the external-data load against area_size. Patch 1 raises
area-size to match the binman section size so test_vbe_vpl keeps passing
once the bound is enforced. The patches are ordered so the test is never
broken in the middle of the series.
Patch 2 adds the missing range check, confining the FIT-supplied
[load_addr, load_addr + len) window to [addr, addr + area_size] before
block numbers and lengths are computed, and applying the same constraint
to fdt_load_addr and fdt_size. The check is written in subtraction-only
form against the trusted area_size so the comparison cannot itself
overflow.
Patch 3 adds two sandbox unit tests under test/boot/ that construct
synthetic FITs with out-of-range data-position and oversized data-size,
write them to mmc1, and confirm vbe_read_fit() returns -E2BIG for each
before issuing the follow-up blk_read().
Deferring the external-data blk_read() until after the phase has been
signature-verified would be a stronger structural fix and was discussed
on the v1 thread. Simon confirmed the bounded read is the right first
step and that the verify-then-load change should be a separate series,
so this v3 stays scoped to the bound.
Link: https://lore.kernel.org/r/[email protected]
|
|
The firmware1 node in test.dts declares area-size = 0xe00000 (14 MiB)
but the binman fw-update section in sandbox_vpl.dtsi is 0x2000000
(32 MiB) and the FIT inside it carries ~16 MiB of external data
(spl + u-boot subimages). The FIT therefore extends past the
declared firmware area, contradicting the documented contract of
vbe_read_fit() that the FIT must fit within @area_size.
The mismatch was tolerated because no caller actually bounded the
external-data load against area_size. Bring the devicetree in line
with the binman section size so the FIT extent stays within the
trusted firmware area, in preparation for vbe_read_fit() enforcing
that bound.
state-offset and version-offset are left as-is; they were already
inside the FIT data region and are not exercised by test_vbe_vpl.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Aristo Chen <[email protected]>
|
|
Paresh Bhagat <[email protected]> says:
This series adds support for DM firmware reserved memory fixup in device
tree for K3 SoCs that use separate DM firmware (K3_DM_FW enabled).
The series includes:
1. Fix for phandle corruption in FDT reserved memory fixup
2. Enable OF_SYSTEM_SETUP for AM62D2 to allow device tree fixups
3. Add Kconfig options for DM firmware reserved memory for other K3 SoCs
4. Add DM reserved memory fixup implementation
The main issue being addressed is that the current reserved DDR carveout
for DM firmware in device tree is insufficient to accommodate the DM
firmware binary on AM62A7, and potentially other K3 SoCs in the future.
Currently, the size is only modified for AM62A7 SoC. For rest of SocS
existing values from device tree is taken.
For vendor boards, please verify boot and check for errors if any.
This series depends on dts update for effected devices. If "dm" node is
not found then the existing mechanism creates a new node with same
address, which cause memory overlap issue.
Link: https://lore.kernel.org/r/[email protected]
|
|
Add support for fixing up DM firmware reserved memory in the kernel
device tree for K3 SoCs that use separate DM firmware.
The fixup uses the CONFIG_K3_DM_FW_RESERVED_ADDR and
CONFIG_K3_DM_FW_RESERVED_SIZE Kconfig options to update the
reserved-memory node with the correct DM firmware carveout.
Note that the fixup needs DM reserved memory node is to be renamed in
dts. Example memory@9c900000 → dm@9c900000
Signed-off-by: Paresh Bhagat <[email protected]>
Reviewed-by: Neha Malcom Francis <[email protected]>
|
